參數(shù)資料
型號(hào): UPD72012GB-004-3B4
廠商: NEC Corp.
英文描述: HUB CONTROLLER FOR UNIVERSAL SERIAL BUS
中文描述: 集線器控制器通用串行總線
文件頁數(shù): 22/36頁
文件大?。?/td> 414K
代理商: UPD72012GB-004-3B4
22
Data Sheet S13918EJ3V0DS
μ
PD72012
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Rating
Unit
Power supply voltage
V
DD
–0.5 to +4.6
V
USB buffer
UD0, UD1, D10 to D50, D11 to D51
–0.5 to +4.6
V
Clock input buffer
X1, CLK/X2
–0.5 to +6.6
V
5 V Schmitt input buffer
RST, CS1 to CS5
–0.5 to +6.6
V
Input voltage
V
I
5 V input buffer
CLKSEL, PSSEL, PVSEL
–0.5 to +4.6
V
USB buffer
UD0, UD1, D10 to D50, D11 to D51
–0.5 to +4.6
V
Open drain output buffer
PP1 to PP5
–0.5 to +6.6
V
Output voltage
V
O
5 V output buffer
OSL
–0.5 to +6.6
V
Output current
I
O
100
mA
Operating ambient temperature
T
A
0 to +70
°
C
Storage temperature
T
stg
–65 to +150
°
C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (T
A
= 0 to +70
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Power supply voltage
V
DD
3.0
3.3
3.6
V
High level input voltage
V
IH
2.0
V
DD
V
Low level input voltage
V
IL
USB pin
UD0, UD1, D10 to D50, D11 to D51
0
0.8
V
High level input voltage
V
IH
2.3
5.5
V
Low level input voltage
V
IL
5 V Schmitt input pin
RST, CS1 to CS5
0
0.8
V
Input rise time for RST
tr
0.3 V to 2.7 V
10
ms
High level input voltage
V
IH
2.0
5.5
V
Low level input voltage
V
IL
5 V input pin
CLKSEL, PSSEL, PVSEL
0
0.8
V
High level input voltage
V
IH
2.3
5.5
V
Low level input voltage
V
IL
Clock input pin (at 48 MHz input)
X1, CLK/X2
0
0.8
V
Oscillator input (+100 ppm)
48.00
MHz
Clock input frequency
f
CK
Oscillator input (+50 ppm)
4.0
MHz
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