參數(shù)資料
型號(hào)： uPD72107CW
廠商： NEC Corp.
英文描述： LAP-B CONTROLLER(Link Access Procedure Balanced mode)
中文描述： 鱲- B控制器（鏈路訪問(wèn)過(guò)程平衡模式）
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 182K
代理商： UPD72107CW
20
μ
PD72107
Serial block (2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RxC cycle time
t
CYR
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
30.3
125
ns
1000
RxC low-level time
t
SSRL
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
ns
RxC high-level time
t
SSRH
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
ns
RxC rise time
t
SRR
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
ns
10
RxC fall time
t
SRF
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
ns
10
Transmit/receive data cycle
t
CYD
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
500
2000
ns
16000
TxC low-level time
t
TCTCL
When on-chip DPLL is used
0.5t
CYD
–25
ns
TxC high-level time
t
TCTCH
0.5t
CYD
–25
ns
TxD delay time (vs. TxC
↓
)
t
DTCTD
50
ns
TxD hold time (vs. TxC
↑
)
t
HTCTD
0.5t
CYD
–25
ns
Serial clock (when on-chip DPLL is used)
t
CYR
t
SSRL
t
SRF
t
TCTCL
t
DTCTD
t
TCTCH
t
HTCTD
t
CYD
t
SRR
t
SSRH
TxC
TxD
RxC
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