參數(shù)資料
型號(hào)： UPD7228A
廠商： NEC Corp.
英文描述： 1/8, 1/16 DUTY LCD CONTROLLER/DRIVER
中文描述： 1 / 8，1 / 16稅LCD控制器/驅(qū)動(dòng)
文件頁(yè)數(shù)： 38/64頁(yè)
文件大?。?/td> 314K
代理商： UPD7228A
Data Sheet S10299EJ4V0DS00
38
μ
PD16434
8. RESET OPERATION
The
μ
PD16434 is initialized as follows, when a high level is input to the RESET pin :
The chip address compare data (compared with CA1, CA0 inputs) is initialized to 00.
In a multi-chip configuration, /BUSY output operation will differ, depending on whether CA1 and CA0 of the chip
are 00 (coinciding address) or not (non-coinciding address) (refer to Figure 8–1).
When CA1, CA0 = 00
: Sets /BUSY output to low, if /CS = 0. If /CS = 1, sets /BUSY output to high
impedance.
Other than 00
: Sets /BUSY output to high impedance, regardless of /CS input.
In a single chip configuration, /BUSY output operation is the same as that when CA1 and CA0 are 00.
All processing operations (command/data processing, reading timing signal and display data to the row and
column driver) are stopped.
V
LC3
level DC current is output from each LCD drive signal output pin (C0 to C41, R15/C42 to R8/C49, R0/R8
to R7/R15).
The internal functions are set as follows (to the same conditions as when these commands are executed) :
SWM (I
1
I
0
= 00)
: Auto-increment mode
LDPI (D
6
to D
0
= 0000000)
: Data pointer is cleared to 0
SMM (M
2
to M
0
= 000)
: 8-time-divisions, R0/R8 to R7/R15 pins serve as R0 to R7 pins, SYNC pin is set in
the input mode, the data memory is set to bank 0.
SFF (F
2
to F
0
= 000)
: Frame frequency is set to f
CL
/2
14
.
The byte transfer end counter is cleared.
If the
μ
PD16434 is in the standby mode, the standby mode is maintained.
The data memory contents become undefined.
When the high level input to the RESET pin is returned to low, the operation becomes possible, according to the
initialized contents. In addition, the next processing will be performed at the falling edge of the RESET signal. The display
output will be the same as when the DISP OFF is executed.
The interface specification code (serial/parallel specification, chip address selection function provided/
unprovided) is read from the D2(CAE) and D1(P, /S) pins.
A chip, whose CA1 and CA0 values are 0, becomes selected state.
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