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參數(shù)資料
| 型號(hào)： | UPD72871F1 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 1-CHIP OHCI HOST CONTROLLER |
| 中文描述： | IEEE1394連接1 - OHCI主機(jī)控制器芯片 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 311K |
| 代理商： | UPD72871F1 |
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Preliminary Data Sheet S13925EJ2V0DS00
19
μ
PD72870,72871
Table
2-1. Bit Field Description (2/3)
Field
Size
R/W
Reset value
Description
Extended
3
R
111
Shows the extended register map.
Total_ports
4
R
0011
or
0001
Supported port number.
0011: 3port (
μ
PD72870)
0001: 1port (
μ
PD72871)
Max_speed
3
R
010
Indicate the maximum speed that this node supports.
010: 98.304, 196.608 and 393.216 Mbps
Delay
4
R
0010
Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec
Link_active
1
R/W
1
Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS.
State will be referred to “L bit” of Self-ID Packet#0.
The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It
is an internal signal in the
μ
PD72870,72871.
Contender
1
R/W
See
Description
Contender.
“1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
Jitter
3
R
010
The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec
Pwr_class
3
R/W
See
Description
Power class.
Please refer to IEEE1394 -1995 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
The reset data will be determined by PC0-PC2 Pin status.
Resume_int
1
R/W
0
Resume interrupt enable. When set to 1, if any one port does resume, the
Port_event bit becomes 1.
ISBR
1
R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3
μ
sec
Returns to 0 at the beginning of the bus reset.
Loop
1
R/W
0
Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Pwr_fail
1
R/W
0
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Timeout
1
R/W
0
Arbitration state machine time-out.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
#
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