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參數(shù)資料
| 型號： | UPD750104CU |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 17/80頁 |
| 文件大?。?/td> | 525K |
| 代理商： | UPD750104CU |
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17
μ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Figure 5-1. Program Memory Map (in
μ
PD750104)
Note
Can be used only in the Mk
ΙΙ
mode.
Remark
In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the 8 low-order bits of the PC changed.
0 0 0 H
Address
7
6
5
4
MBE RBE
0
0
Internal reset start address
(high-order 4 bits)
0
0 0 2 H MBE RBE
0
0
INTBT/INT4
(high-order 4 bits)
start address
0 0 4 H MBE RBE
0
0
INT0
(high-order 4 bits)
start address
0 0 6 H MBE RBE
0
0
INT1
(high-order 4 bits)
start address
0 0 8 H MBE RBE
0
0
INTCSI
(high-order 4 bits)
start address
0 0 A H MBE RBE
0
0
INTT0
(high-order 4 bits)
start address
0 0 C H MBE RBE
0
0
INTT1
(high-order 4 bits)
start address
0 2 0 H
0 7 F H
0 8 0 H
7 F F H
8 0 0 H
F F F H
GETI instruction reference table
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
! faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1
Note
CALLA !addr1
Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
-15 to -1,
+2 to +16
BRCB
!caddr
instruction
branch
address
Branch destination
address and
subroutine entry
address when
GETI instruction
is executed
Internal reset start address
INTBT/INT4
start address
INT0
start address
INT1
start address
INTCSI
start address
INTT0
start address
INTT1
start address
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