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參數(shù)資料
| 型號(hào)： | UPD750108GB |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 58/80頁(yè) |
| 文件大?。?/td> | 525K |
| 代理商： | UPD750108GB |
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μ
PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
58
AC CHARACTERISTICS (T
A
= -40 to +85
°
C, V
DD
= 1.8 to 5.5 V)
CPU clock cycle
time
Note 1
(minimum
instruction execution time
= 1 machine cycle)
TI0 input frequency
TI0 input high/low level
width
Interrupt input high/low
level width
RESET low level width
RC oscillator frequency
IM02 = 0
IM02 = 1
Notes 1.
When the main system clock is used, the
cycle time of the CPU clock (
Φ
) (minimum
instruction execution time) depends on the
time constants of connected resistors (R)
and capacitors (C) and the processor clock
control register (PCC).
When the subsystem clock is used, the cycle
time of the CPU clock (
Φ
) (minimum instruc-
tion execution time) depends on the fre-
quency of the connected resonator (and ex-
ternal clock), the system clock control regis-
ter (SCC), and the processor clock control
register (PCC).
The figure on the right side shows the cycle
time t
CY
characteristics for the supply voltage
V
DD
during main system clock operation.
2.
This value becomes 2t
CY
or 128/f
CC
accord-
ing to the setting of the interrupt mode reg-
ister (IM0).
t
CY
f
TI
t
TIH
,
t
TIL
t
INTH
,
t
INTL
t
RSL
f
CC
Conditions
MIN.
TYP.
MAX.
Unit
Operated by main system clock pulse
2.0
128
μ
s
Operated by subsystem clock pulse
114
122
125
μ
s
V
DD
= 2.7 to 5.5 V
0
1
MHz
0
275
kHz
V
DD
= 2.7 to 5.5 V
0.48
μ
s
1.8
μ
s
INT0
Note 2
μ
s
10
μ
s
INT1, INT2, and INT4
10
μ
s
KR0 to KR7
10
μ
s
10
μ
s
MHz
MHz
Parameter
Symbol
V
DD
= 2.7 to 5.5 V
V
DD
= 2.7 to 5.5 V
1.00
1.00
1.30
1.30
0.90
0.55
R = 22 k
,
C = 22 pF
1
1.8 2
3
4
5 5.5 6
0
0.5
1
2
3
4
5
6
128
t
CY
vs. V
DD
(Main system clock in operation)
C
C
μ
Power supply voltage V
DD
[V]
Operation guaranteed
range
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