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參數(shù)資料
| 型號： | UPD75068GB |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 14/68頁 |
| 文件大小： | 640K |
| 代理商： | UPD75068GB |
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14
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
4. MEMORY CONFIGURATION
Program memory (ROM) ..... 4096
×
8 bits (0000H to 0FFFH) :
μ
PD75064
..... 6016
×
8 bits (0000H to 177FH) :
μ
PD75066
..... 8064
×
8 bits (0000H to 1F7FH) :
μ
PD75068
0000H to 0001H : Vector table in which the program start address by reset is stored
0002H to 000BH : Vector table in which the program start address by interrupt is stored
0020H to 007FH : Table area to be referenced by GETI instruction
Data memory
Data area
Peripheral hardware area ..... 128
×
4 bits
..... 512
×
4 bits
(000H to 1FFH)
(F80H to FFFH)
Figure 4-1. Program Memory Map
(a)
μ
PD75064
MBE
0
0
7
6
5
0000H
Address
MBE
0
0
0002H
MBE
0
0
0004H
MBE
0
0
0006H
MBE
0
0
0008H
MBE
0
0
000AH
007FH
0080H
0020H
07FFH
0800H
0FFFH
0
Internal reset start address (high-order 4 bits)
Internal reset start address (low-order 8 bits)
INTBT/INT4 start address (high-order 4 bits)
INTBT/INT4 start address (low-order 8 bits)
INT0 start address (high-order 4 bits)
INT0 start address (low-order 8 bits)
INT1 start address (high-order 4 bits)
INT1 start address (low-order 8 bits)
INTCSI start address
(high-order 4 bits)
INTCSI start address (low-order 8 bits)
INTT0 start address (high-order 4 bits)
INTT0 start address (low-order 8 bits)
GETI instruction reference table
CALL ! addr
instruction
subroutine entry
address
BR $addr
instruction
relative branch
address
(–15 to –1,
+2 to +16)
CALLF
! faddr
instruction
entry
address
BRCB
! caddr
instruction
branch
address
Branch destination
address specified
by GETI instruction,
Subroutine entry
address
0
0
0
0
0
0
4
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