28
μ
PD75112(A), 75116(A)
Table 8-1 Hardware Statuses after Reset
* 1:
Power-on reset ................... 1
RESET input in operation ... Undefined
2:
Data at addresses 0F8H to 0FDH of the data memory becomes undefined due to RESET input.
PWS
Basic interval timer
Timer/ event
counter
(n = 0, 1)
Serial
interface
RESET Input in Power-On
Reset or Operation
same as left
Undefined
0
0
same as left
Undefined
Undefined
Undefined
0, 0
Undefined
0
0
FFH
0
0, 0
Undefined
0
0
0
Reset (0)
0
0
0, 0
Off
Clear (0)
0
Undefined
0
1 or undefined
*2
0
Clock
generator,
clock
output
circuit
Interrupt
Digital
port
Analog
port
RESET Input in Standby Mode
Lower 6 bits of address 0000H of the program memory are set to
PC
13
to PC
8
and the content of address 0001H is set to PC
7
to PC
0
.
Hold
0
0
Bits 6 and 7 of address 0000H of the program memory are set to
RBE and MBE, respectively.
Undefined
Hold
*1
Hold
0, 0
Undefined
0
0
FFH
0
0, 0
Hold
0
0
0
Reset (0)
0
0
0, 0
Off
Clear (0)
0
Undefined
0
Hold
0
Hardware
Program counter (PC)
Carry flag (CY)
Skip flag (SK0 to SK2)
Interrupt status flag (IST0, 1)
Bank enable flags (MBE, RBE)
Stack pointer (SP)
Data memory (RAM)
General registers (X, A, H, L, D, E, B, C)
Bank select registers (MBS, RBS)
Counter (BT)
Mode register (BTM)
Counter (Tn)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOFn
Shift register (SIO)
Mode register (SIOM)
Processor clock control
register (PCC)
Clock output mode
register (CLOM)
Interrupt request flag (IRQ
×××
)
Interrupt enable flag (IE
×××
)
Priority select resister (IPS)
INT0, 1 mode resisters (IM0, IM1)
Output buffer
Output latch
Input/output mode registers
(PMGA, PMGB, PMGC)
PTH00 to PTH03 input latches
Mode register (PTHM)
Power-on flag (PONF)
Bit sequential buffers (BSB0 to BSB3)