參數(shù)資料
型號(hào)： UPD75206
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 12/62頁(yè)
文件大小： 489K
代理商： UPD75206
12
μ
PD75206
4.
μ
PD75206 ARCHITECTURE AND MEMORY MAP
The
μ
PD75206 has the following three architectural features.
Data memory bank configuration:
Static RAM (320 words x 4 bits)
Display data memory (49 words x 4 bits)
Peripheral hardware (128 x 4 bits)
General register bank configuration: 8 x 4 banks (Operated in 4 bits)
4 x 4 banks (Operated in 8 bits)
Memory mapped I/O
Figures 4-1, 4-2 shows memory maps of
μ
PD75206.
Remarks
In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
6
INTBT/INT4 Start Address
INTBT/INT4 Start Address
INT0 Start Address
INT0 Start Address
INT1 Start Address
INT1 Start Address
Internal Reset Start Address (Most Significant 5 Bits)
Internal Reset Start Address (Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
INTSIO Start Address
INTSIO Start Address
INTT0 Start Address
INTT0 Start Address
INTTPG Start Address
INTTPG Start Address
INTKS Start Address
INTKS Start Address
GETI Instruction Reference Table
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0000H
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
177FH
Address
7
RBE
0
CALLF
!faddr
Instruction
Entry Address
BRCB
!caddr
Instruction
Branch Address
BR !addr
Instruction
Branch Address
CALL !addr
Instruction
Subroutine Entry
Address
BR $addr Instruction
Relative Branch
Address
(-15 to -1 and +2 to +16)
Branch Destination
Address and
Subroutine Entry
Address to be Set
by GETI Instruction
0
0
0
0
0
0
0
0
5
Fig. 4-1 Program Memory Map
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