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81
μ
PD753104, 753106, 753108
APPENDIX A.
μ
PD75308B, 753108 AND 75P3116 FUNCTIONAL LIST
Parameter
μ
PD75308B
μ
PD753108
μ
PD75P3116
Program memory
Mask ROM
0000H to 1F7FH
(8064 x 8 bits)
Mask ROM
0000H to 1FFFH
(8192 x 8 bits)
One-time PROM
0000H to 3FFFH
(16384 x 8 bits)
Data memory
000H to 1FFH
(512 x 4 bits)
CPU
75X Standard
75XL CPU
Instruction
execution
time
When main system clock is
selected
0.95, 1.91, 15.3
μ
s
(during 4.19-MHz operation)
0.95, 1.91, 3.81, 15.3
μ
s (during 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7
μ
s (during 6.0-MHz operation)
When subsystem clock is
selected
122
μ
s (32.768-kHz operation)
Stack
SBS register
None
SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection
Stack area
000H to 0FFH
000H to 1FFH
Subroutine call instruction
stack operation
2-byte stack
When Mk I mode: 2-byte stack
When Mk II mode: 3-byte stack
Instruction
BRA !addr1
CALLA !addr1
Unavailable
When Mk I mode: unavailable
When Mk II mode: available
MOVT XA, @BCDE
MOVT XA, @BCXA
BR BCDE
BR BCXA
Available
CALL !addr
3 machine cycles
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles
CALLF !faddr
2 machine cycles
Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles
I/O port
CMOS input
8
8
CMOS input/output
16
20
Bit port output
8
0
N-ch open-drain input/output
8
4
Total
40
32
LCD controller/driver
Segment selection: 24/28/32
Segment selection: 16/20/24 segments
(can be changed to CMOS input/output port in 4 time-unit;
max. 8)
segments
(can be changed to CMOS
input/output port in 4 time-
unit; max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by using
mask option.
No on-chip split resistor for
LCD driver
Timer
3 channels
Basic interval timer:
1 channel
8-bit timer/event counter:
1 channel
Watch timer: 1 channel
5 channels
Basic interval timer/watchdog timer: 1 channel
8-bit timer/event counter: 3 channels
(can be used as 16-bit timer/event counter)
Watch timer: 1 channel