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參數(shù)資料
| 型號： | UPD753108GK |
| 廠商： | NEC Corp. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 40/90頁 |
| 文件大?。?/td> | 547K |
| 代理商： | UPD753108GK |
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40
μ
PD753104, 753106, 753108
8. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
μ
PD753108.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP mode
HALT mode
Set instruction
STOP instruction
HALT instruction
System clock when set
Settable only when the main system
clock is used.
Settable both by the main system clock
and subsystem clock.
Operation
status
Clock generator
Main system clock stops oscillation.
Only the CPU clock
Φ
halts (oscillation
continues).
Basic interval timer/
watchdog timer
Operation stops.
Operable only when the main system
clock is oscillated.
BT mode : IRQBT is set in the
reference time interval
WT mode: Reset signal is generated
by BT overflow
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable only when an external SCK
input
is selected as the serial clock or
when the
main system clock is oscillated.
Timer/event counter
Operable only when a signal input to the
TI0 to TI2 pins is specified as the count
clock.
Operable only when a signal input to the
TI0 to TI2 pins is specified as the count
clock or when the main system clock is
oscillated.
Watch timer
Operable when f
XT
is selected as the
count clock.
Operable.
LCD controller/driver
Operable only when f
XT
is selected as the Operable.
LCDCL.
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operated
Note
.
CPU
The operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the interrupt
enable flag or RESET signal input.
Note
Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection
mode register (IM0).
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