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37
μ
PD75312B, 75316B
(3) Description of addressing area field symbols
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
Data Memory
Addressing
MB = MBE MBS (MBS = 0 to 3, 15)
MB = 0
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0 to 3, 15)
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
addr = 0000H to 2F7FH
addr = 0000H to 3F7FH
addr = (Current PC) –15 to (Current PC) –1,
(Current PC) +2 to (Current PC) + 16
caddr = 0000H to 0FFFH (PC
13
= 0, PC
12
= 0)or
1000H to 1FFFH (PC
13
= 0, PC
12
= 1) or
2000H to 2F7FH (PC
13
= 1, PC
12
= 0)
caddr = 0000H to 0FFFH (PC
13
= 0, PC
12
= 0) or
1000H to 1FFFH (PC
13
= 0, PC
12
= 1) or
2000H to 2FFFH (PC
13
= 1, PC
12
= 0) or
3000H to 3F7FH (PC
13
= 1, PC
12
= 1)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
Program Memory
Addressing
μ
PD75312B
μ
PD75316B
Remarks
1.
2.
3.
4.
MB indicates the accessible memory bank.
For *2, MB = 0 without regard to MBE and MBS.
For *4 and *5, MB = 15 without regard to MBE and MBS.
*6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field
S shows the number of machine cycles required when skip is performed by an instruction with skip. The value
of S changes as follows:
No skip ....................................................................................................................................................................... S = 0
When instruction to be skipped is 1-byte or 2-byte instruction......................................................................... S = 1
When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction)............................. S = 2
Caution One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= t
CY
) of the CPU clock
Φ
. Three times can be selected by PCC
setting.
μ
PD75312B
μ
PD75316B