參數(shù)資料
型號(hào)： UPD75316A
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 21/62頁(yè)
文件大小： 577K
代理商： UPD75316A
μ
PD75312(A), 75316(A)
21
5.2
CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and
system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
0.95
μ
s/1.91
μ
s/15.3
μ
s (main system clock: 4.19 MHz)
122
μ
s (subsystem clock: 32.768 kHz)
Remarks
1: f
X
= Main system clock frequency
2: f
XT
= Subsystem clock frequency
3: PCC: Processor clock control register
4: SCC: System clock control register
5:
*:
instruction execution.
6: One clock cysle (t
CY
) of
Φ
is one machine cycle of an instruction. For t
CY
, refer to AC
characteristics in 11. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
V
DD
V
DD
XT1
XT2
X1
X2
f
XT
f
X
LCD controller
/driver
Watch timer
Subsystem
clock
oscillator
Main system
clock
oscillator
1/2 1/16
1/8 to 1/4096
Frequency divider
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· INT0 noise rejecter circuit
· Clock output circuit
I
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
HALT*
STOP*
4
PCC2, PCC3
clear signal
STOP F/F
Q
S
R
Q
S
R
HALT F/F
Oscillator
disable
signal
Frequency
divider
1/4
S
S
Φ
· CPU
· INT0 noise
rejecter circuit
· Clock output
circuit
Wait release
signal from BT
RESET signal
Standby release
signal from interrupt
control circuit
#
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