60
μ
PD753204, 753206, 753208
DC CHARACTERISTICS (T
A
= –40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
LCD drive voltage
V
LCD
VAC0 = 0
T
A
= –40 to +85C
2.7
V
DD
V
T
A
= –10 to +85C
2.2
V
DD
V
VAC0 = 1
1.8
V
DD
V
VAC current
Note 1
I
VAC
VAC0 = 1, V
DD
= 2.0 V
±
10%
1
4
μ
A
LCD split resistor
Note 2
R
LCD1
50
100
200
k
R
LCD2
5
10
20
k
LCD output voltage
deviation
Note 3
(common)
V
ODC
l
O
=
±
1.0
μ
A
V
LCD0
= V
LCD
V
LCD1
= V
LCD
×
2/3
V
LCD2
= V
LCD
×
1/3
1.8 V
≤
V
LCD
≤
V
DD
0
±
0.2
V
LCD output voltage
deviation
Note 3
(segment)
V
ODS
l
O
=
±
0.5
μ
A
0
±
0.2
V
Supply current
Note 4
I
DD1
6.0 MHz
Crystal oscillation
C1 = C2 = 22 pF
V
DD
= 5.0 V
±
10%
Note 5
1.9
6.0
mA
V
DD
= 3.0 V
±
10%
Note 6
0.4
1.3
mA
I
DD2
HALT mode
V
DD
= 5.0 V
±
10%
0.72
2.1
mA
V
DD
= 3.0 V
±
10%
0.27
0.8
mA
I
DD1
4.19 MHz
Crystal oscillation
C1 = C2 = 22 pF
V
DD
= 5.0 V
±
10%
Note 5
1.5
4.0
mA
V
DD
= 3.0 V
±
10%
Note 6
0.25
0.75
mA
I
DD2
HALT mode
V
DD
= 5.0 V
±
10%
0.7
2.0
mA
V
DD
= 3.0 V
±
10%
0.23
0.7
mA
I
DD3
STOP mode
V
DD
= 5.0 V
±
10%
0.05
10
μ
A
V
DD
= 3.0 V
±
10%
0.02
5
μ
A
T
A
= 25C
0.02
3
μ
A
Notes 1.
Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1
μ
A.
2.
Either R
LCD1
or R
LCD2
can be selected by the mask option.
3.
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (V
LCDn
; n = 0, 1, 2).
4.
Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
5.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
6.
When PCC is set to 0000 and the device is operated in the low-speed mode.