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參數(shù)資料
| 型號： | UPD75402 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | UPD75402 |
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24
μ
PD75402A(A)
Table 8-1 Hardware Statuses after Reset Operations
Hardware
Program counter (PC)
PSW
Carry flag (CY)
Skip flag (SK0 - SK2)
Interrupt status flag (IST0)
Stack pointer (SP)
Data memory (RAM)
General register (X, A, H, L)
RESET input during operations
Set the three low-order bits of
address 000H in program
memory in PC bits 10 to 8 and
set the contents of address
001H in PC bits 7 to 0.
Undefined
0
0
Undefined
Undefined
Undefined
Undefined
0
Undefined
0
0
Undefined
0
0
Reset (0)
0
0
0
Off
Cleared (0)
0
0
Used as inputs
High level when pull-up
resistor is built in
High impedance when
open drain is used in the
internal circuit
RESET input in standby mode
Set the three low-order bits of
address 000H in program
memory in PC
bits 10 to 8 and
set the contents of address
001H in PC bits 7 to 0.
Retained
0
0
Undefined
Retained
Note
Retained
Undefined
0
Retained
0
0
Retained
0
0
Reset (0)
0
0
0
Off
Cleared (0)
0
0
Used as inputs
High level when pull-up
resistor is built in
High impedance when
open drain is used in the
internal circuit
Counter (BT)
Mode register (BTM)
Shift register (SIO)
Operation mode register (CSIM)
SBI control register (SBIC)
Slave address register (SVA)
Processor clock control register
(PCC)
Clock output mode register
(CLOM)
Interrupt request flag (IRQ
×××
)
Interrupt enable flag (IE
×××
)
Interrupt master enable flag
(IME)
INT0 mode register (IM0)
Output buffer
Output latch
I/O mode register
(PMGA, PMGB)
Pull-up resistor specification
register (POGA)
P00 - P03, P10, P12, P20 - P23,
P30 - P33, P60 - P63
P50 - P53
Basic interval
timer
Serial
interface
Clock genera-
tor and clock
output circuit
Interrupt
Digital I/O
port
States of pins
Note
Data in the data memory whose addresses are 38H to 3DH is not defined when the standby mode
is released by the RESET input signal.
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