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28
μ
PD75402A(A)
Instruc-
tion
group
Memory
bit
manipu-
lation
instruc-
tion
Branch
instruc-
tion
Subrou-
tine
stack
control
instruc-
tion
Interrupt
control
instruc-
tion
Input/
output
instruc-
tion
CPU
control
instruction
Mne-
monic
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
BR
BRCB
CALLF
RET
RETS
RETI
PUSH
POP
EI
DI
IN
OUT
HALT
STOP
NOP
Number
of
bytes
2
2
2
2
2
2
2
2
2
2
2
2
–
1
2
2
1
1
1
1
1
2
2
2
2
2
2
2
2
1
Skip
condition
(mem.bit) = 1
(fmem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(
fmem.bit) = 1
Uncondition-
ally
Address-
ing area
*2
*3
*2
*3
*2
*3
*2
*3
*3
*3
*3
*3
*4
*5
*6
*7
Ma-
chine
cycle
2
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2
2
2
–
2
2
2
3
3 + S
3
1
1
2
2
2
2
2
2
2
2
1
Operand
mem.bit
fmem.bit
mem.bit
fmem.bit
mem.bit
fmem.bit
mem.bit
fmem.bit
fmem.bit
CY, fmem.bit
CY, fmem.bit
CY, fmem.bit
addr
$addr
!caddr
!faddr
rp
rp
IE
×××
IE
×××
A, PORTn
PORTn, A
Operation
(mem.bit)
←
1
(fmem.bit)
←
1
(mem.bit)
←
0
(fmem.bit)
←
0
Skip if (mem.bit) = 1
Skip if (fmem.bit) = 1
Skip if (mem.bit) = 0
Skip if (fmem.bit) = 0
Skip if (fmem.bit) = 1 and clear
CY
←
CY
∧
(fmem.bit)
CY
←
CY
∨
(fmem.bit)
CY
←
CY
∨
(fmem.bit)
PC
10-0
←
addr
(The assembler selects an
appropriate instruction from the
BRCB !caddr and BR $addr
instructions.)
PC
10-0
←
addr
PC
10-0
←
caddr
(SP – 4)(SP – 1)(SP – 2)
←
0, PC
10-0
(SP – 3)
←
0000
PC
10-0
←
faddr, SP
←
SP – 4
×
, PC
10-0
←
(SP)(SP + 3)(SP + 2)
SP
←
SP + 4
×
, PC
10-0
←
(SP)(SP + 3)(SP + 2)
SP
←
SP + 4, then skip unconditionally
×
, PC
10-0
←
(SP)(SP + 3)(SP + 2)
PSW
←
(SP + 4)(SP + 5), SP
←
SP + 6
(SP – 1)(SP – 2)
←
rp, SP
←
SP – 2
rp
←
(SP + 1)(SP), SP
←
SP + 2
IME (IPS.3)
←
1
IE
××× ←
1
IME (IPS.3)
←
0
IE
×××
←
0
A
←
PORTn (n = 0 - 3, 5, 6)
PORT n
←
A (n = 2, 3, 5, 6)
Set HALT mode (PCC.2
←
1)
Set STOP mode (PCC.3
←
1)
No operation