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參數(shù)資料
| 型號： | UPD75402ACTA |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大小： | 515K |
| 代理商： | UPD75402ACTA |
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20
μ
PD75402A(A)
6. INTERRUPT FUNCTION
The
μ
PD75402A(A) has three interrupt sources and each of them has the interrupt vector table.
The
μ
PD75402A(A) is also provided with one edge-sensitive testable input signal.
When a vectored interrupt request is issued, the PC and PSW are saved in the stack, and the contents of
the vector table which corresponds to the issued vectored interrupt are set in the PC as a start address. The
program branches to the interrupt service routine. These operations are performed automatically by the
hardware.
The flag is set by detecting the edge of the testable input signal, but a vectored interrupt request is not
issued.
During execution of the interrupt service routine, the
μ
PD75402A(A) does not accept the other interrupt
requests. Unlike the other 75X series, the
μ
PD75402A(A) cannot handle multiple interrupts.
The interrupt control circuit of the
μ
PD75402A(A) has the following functions.
Vectored interrupt function under hardware control which can determine whether to accept an interrupt
by an interrupt enable flag (IE
×××
) and an interrupt master enable flag (IME).
Any interrupt start address can be set.
Test function of an interrupt request flag (IRQ
×××
) (Software can confirm that an interrupt occurs.)
Release of the standby (HALT) mode (An interrupt to be released by an interrupt enable flag can be selected
from interrupts other than INT0.)
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