參數(shù)資料
型號(hào)： UPD754244GS
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 4位單晶片微控制器
文件頁(yè)數(shù)： 52/88頁(yè)
文件大?。?/td> 416K
代理商： UPD754244GS
52
μ
PD754144, 754244
μ
PD754144
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time
Note1
t
CY
2.0
4.0
128
μ
s
(Minimum instruction execution
time = 1 machine cycle)
RC oscillation frequency
f
CC
R = 22 k
,
V
DD
= 3.6 to 6.0 V
0.9
1.0
Note 2
1.2
MHz
C = 22 pF
V
DD
= 2.2 to 3.6 V
0.75
1.0
Note 2
1.15
MHz
V
DD
= 1.8 to 3.6 V
0.5
1.0
Note 2
1.15
MHz
V
DD
= 1.8 to 6.0 V
0.5
1.0
Note 2
1.2
MHz
R = 5.1 k
,
V
DD
= 3.6 to 6.0 V
0.91
1.0
Note 2
1.1
MHz
C = 120 pF
V
DD
= 2.2 to 3.6 V
0.76
1.0
Note 2
1.05
MHz
V
DD
= 1.8 to 3.6 V
0.51
1.0
Note 2
1.05
MHz
V
DD
= 1.8 to 6.0 V
0.51
1.0
Note 2
1.1
MHz
Interrupt input high- and
t
INTH
, t
INTL
INT0
IM02 = 0
Note 3
μ
s
low-level width
IM02 = 1
10
μ
s
KR4 to KR7
10
μ
s
RESET low-level width
t
RSL
10
μ
s
Notes 1.
The CPU clock (
Φ
) cycle time (minimum
instruction execution time) is determined
by the time constants of the connected
resistor (R) and capacitor (d) and the pro-
cessor clock control register (PCC). The
figure on the right shows the cycle time t
CY
characteristics against the supply voltage
V
DD
when the system clock is used.
This is the typical value when V
DD
= 3.6 V.
2t
CY
or 128/f
CC
depending on the setting of
the interrupt mode register (IM0).
2.
3.
0.50
Supply voltage V
DD
(V)
1
2
3
4
5
6
1.8
1
2
3
4
5
6
128
(During system clock operation)
t
CY
vs. V
DD
Operation guranteed range
μ
C
C
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