參數(shù)資料
型號(hào)： UPD7554A
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 23/64頁(yè)
文件大?。?/td> 991K
代理商： UPD7554A
23
μ
PD7554A, 7554A(A)
2.12 SERIAL INTERFACE
The serial interface consists of an 8-bit shift register, 3-bit shift mode register, and 3-bit counter. It is used for
input/output of serial data.
Fig. 2-13 Serial Interface Block Diagram
INT0
P00/INT0
P01/SCK
P02/SO
P03/SI
IPL
Note
TSIOAM
Note
TAMSIO
Note
LSB
8–BIT SHIFT REG
MSB
3–BIT CNT
φ
RS F/F
Q
R
S
INTS
SIO
Note
SM3
SHIFT MODE REG
OPL
Note
4
8
8
Internal Bus
Note
Instruction execution
Remarks
1.
φ
indicates the internal clock signal (system clock).
2.
SM3 and INT0 go to the test control circuit.
Input/output of serial data is controlled by the serial clock. The highest bit (bit 7) of the shift register is output
from the SO line at rise of the serial clock (SCK pin signal). At its fall, the contents of the shift register is shifted by
one bit (bit n -> bit n+1) and data on the SI line is loaded to the lowest bit (bit 0) of the shift register.
The 3-bit counter (octal counter) counts serial clock pulses. Wthenever it counts eight clock pulses (on completion
of 1-byte serial data transfer), the counter generates an internal test request signal INTS to set the test request flag
(INT0/S RQF).
Fig. 2-14 Shift Timing
INTS RQF
Setting Timing
SCK
SI
SO
DI
7
DO
7
MSB
DO
6
DO
5
DO
4
DO
3
DO
2
DO
1
DO
0
DI
6
DI
5
DI
4
DI
3
DI
2
DI
1
DI
0
LSB
Remarks
1.
DI: Serial data input
2.
DO: Serial data output
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