參數(shù)資料
型號(hào)： UPD7554ACS
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 13/64頁(yè)
文件大小： 991K
代理商： UPD7554ACS
13
μ
PD7554A, 7554A(A)
1.7
OPERATION OF INPUT/OUTPUT PORTS
(1) P00 to P03 (Port 0)
The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input,
P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output.
To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See
2.10 “CLOCK
CONTROL CIRCUIT”
for details.)
To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1.
The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2
and SM1) of the shift mode register. See
2.12 “SERIAL INTERFACE”
for details.
Even though this port operates using any function other than the port function, execution of the port input
instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time.
(2) P80 to P83 (Port 8)
The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin.
The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs
it to pins P80 to P83.
The SPBL and RPBL instructions
Note
allow bit-by-bit setting and resetting of pins P80 to P83.
Note that P83 is to be selected using a mask option, to serve as one of the connection pins of the resistor R for
RC oscillation (CL2) or as the bit 3 output of the port 8. Thus, the port 8 is a 3-bit output port (P80 to p82) if RC
oscillation is performed, and provides a 4-bit output (P80 to P83) only when an external clock is used.
For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch open-
drain output.
The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a
different supply voltage because the output buffer has a dielectric strength of 9 V.
Contents of the output latch become undefined when the RESET signal is input, then the output becomes high
impedance.
Note
RPBL and SPBL are bit-by-bit setting and resetting instructions. During setting and resetting operations, the
RPBL and SPBL instructionrs allow outputting with each (4-bit) port which contains the specified bits. (The
content of the output latch is output to any pin other than the specified pins.) The content of the output latch
must be initialized with the OPL instruction before executing the RPBL and SPBL instructions.
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