
29
μ
PD7554A, 7554A(A)
4.
RESET FUNCTIONS
The
μ
PD7554A is reset and initialized when the RESET pin inputs a high or active RESET signal as follows:
4.1
DETAILS OF INITIALIZATION
(1) The program counter (PC9-PC0) is cleared to zero.
(2) The skip flags (SK1 and SK0) in the program status word are reset to zero.
(3) The count register in the timer-event counter is cleared to 00H.
(4) The clock control circuit becomes as follows:
Clock mode registers (CM2 and CM1) = 0
1
CP = CL
×
–––––
256
Prescalers 1, 2, and 3 = 0
(5) The shift mode register (SM3 to SM1) is cleared to zero.
→
Shifting of the serial interface is stopped.
→
The port 0 enters the input mode (high impedance).
Note1
→
INT0/S, INTS is selected.
(6) The test request flag (INTT RQF or INT0/S RQF) is reset to zero.
(7) The contents of the data memory and the following registers become undefined:
Stack pointer (SP)
Accumulator (A)
Carry flag (C)
General registers (H and L)
Output latch of each port
(8) The output buffer of every port goes off and has high impedance
Note2
. The I/O port enters the input mode.
Note1.
When the pull-up and pull-down resistors are selected using a mask option, the former has high level and
the latter has low level.
2.
When the pull-up and pull-down resistors are selected in the port 0 using a mask option, the former has
high level and the latter has low level.
When the pull-up resistor is selected in the ports 10 and 11 using a mask option, the resistor has high level.
Caution
When the STANDBY mode is cancelled by the RESET signal, the content of the data memory is retained
without becoming undefined.
When the RESET input is cancelled, the program is executed starting with address 000H. The content of each
register shall either be initialized in the process of the program or reinitialized depending on conditions.