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參數(shù)資料
| 型號： | UPD7566ACS |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 471K |
| 代理商： | UPD7566ACS |
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μ
PD7566A, 7566A(A)
19
2.9 SYSTEM CLOCK GENERATOR
The system clock generator consists of a ceramic oscillator, a 1/2 frequency divider, standby mode (STOP/HALT)
control circuit, and other circuits.
The ceramic oscillator can oscillate, when an external ceramic oscillator is connected across pins CL1 and CL2.
The signal output by the internal ceramic oscillator is a system clock (CL), which is then divided in two to create
a CPU clock ().
The standby mode control circuit mainly consists of a STOP flip-flop and HALT flip-flop.
The STOP flip-flop is set by a STOP instruction, stopping the clock supply. When the ceramic oscillator is
operating, this flip-flop stops the oscillator, setting the microcomputer in the STOP mode.
The STOP flip-flop is reset when a high-level RESET signal is input. As a result, the ceramic oscillator resumes
its operation, and the clocks supply is started, when the RESET signal later goes low.
The HALT flip-flop is set by a HALT instruction, disabling the input of the 1/2 frequency divider, which generates
CPU clock , and thereby stopping only CPU clock (HALT mode).
The HALT flip-flop is reset by the HALT RELEASE or the falling of RESET input (which becomes active when one
of the test request flags has been set), allowing the supply of to be started.
The HALT flip-flop remains set even while the RESET signal is active (high-level), and operates in the same
manner as in the HALT mode.
When Power-ON Reset is performed, the ceramic oscillator starts at the rising edge of the RESET signal. After
the oscillator has started, however, a specific period is required for the oscillator to stabilize. To present the CPU
from malfunctioning due to anstable clock, the HALT flip-flop is set to suppress the CPU clock while the RESET
signal is high. Therefore, the high-level width of the RESET signal must be greater than the time required for the
ceramic oscillator you use to stabilize.
Fig. 2-9 System Clock Generator
Note
indicates that an instruction has been executed.
CL
1
CL
2
Ceramic
oscillator
Oscillation
stops
Q
S
R
Q
S
R
STOP F/F
HALT F/F
1/2
STOP
HALT
RESET (high)
HALT RELEASE
RESET (
)
RESET (
)
(to CPU)
CL (System clock)
Note
Note
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7566CS044 | 制造商:Panasonic Industrial Company 功能描述:IC |
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| UPD75P0016CU-A | 制造商:Renesas Electronics Corporation 功能描述:MCU 4-Bit 75XL CISC 16KB EPROM 2.5V/3.3V/5V 42-Pin SPDIP 制造商:Renesas Electronics 功能描述:75XL 6MHz Cut Tape 制造商:Renesas 功能描述:MCU 4-Bit 75XL CISC 16KB EPROM 2.5V/3.3V/5V 42-Pin SPDIP |
| UPD75P0016GB-3BS-MTX | 制造商:Renesas Electronics 功能描述:MCU 4-Bit 75XL CISC 16KB EPROM 2.5V/3.3V/5V 44-Pin PQFP |
| UPD75P0016GB-3BS-MTX-A | 制造商:Renesas Electronics Corporation 功能描述:MCU 4-bit 75XL CISC 16KB EPROM 2.5V/3.3V/5V 44-Pin PQFP 制造商:Renesas 功能描述:MCU 4-bit 75XL CISC 16KB EPROM 2.5V/3.3V/5V 44-Pin PQFP |
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