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參數(shù)資料
| 型號： | UPD75P108BGF-3BE |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大?。?/td> | 381K |
| 代理商： | UPD75P108BGF-3BE |
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26
μ
PD75P108B
STOP Instruction Execution
V
DD
V
DDDR
RESET
Operating Mode
HALT Mode
Internal RESET Operation
STOP Mode
Data Retention Mode
t
WAIT
t
SREL
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(Ta
= –40 to
+85
°
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
V
DDDR
2.0 6.0 V
Data retention power supply current
*1
Release signal set time
I
DDDR
t
SREL
V
DDDR
= 2.0 V
0.1
10
μ
A
μ
s
0
Release by RESET
Release by interrupt request
2
17
/f
x
*3
ms
ms
Oscillation stabilization wait time
t
WAIT
*
1.
2.
Does not include current flowing in the comparator.
The oscillator stabilization wait time is the time during which CPU operation is halted to prevent
unstable operation when oscillation begins.
Depends on the setting of the basic interval timer mode register (BTM) (table below).
3.
BTM3 BTM2 BTM1 BTM0
WAIT Time (Figure in Parentheses is for f
XX
= 4.19 MHz)
–
0
0
0
2
20
/f
XX
(Approx. 250 ms)
–
0
1
1
2
17
/f
XX
(Approx. 31.3 ms)
–
1
0
1
2
15
/f
XX
(Approx. 7.82 ms)
–
1
1
1
2
13
/f
XX
(Approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
STOP Instruction Execution
V
DD
V
DDDR
Standby Release Signal
(Interrupt Request)
Operating Mode
HALT Mode
STOP Mode
Data Retention Mode
t
WAIT
t
SREL
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