參數(shù)資料
型號： UPD75P3018AGK-BE9
廠商： NEC Corp.
英文描述： LJT 46C 40#20 4#16 2#8(COAX)
中文描述： 4位單片機
文件頁數(shù)： 36/64頁
文件大?。?/td> 356K
代理商： UPD75P3018AGK-BE9
PD75P3018A
41
Data Sheet U11917EJ2V0DS00
SBI mode (SCK ... internal clock output (master)): (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY3
VDD = 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-/low-level width
tKL3, tKH3
VDD = 2.7 to 5.5 V
tKCY3/2–50
ns
tKCY3/2–150
ns
SB0, 1 setup time
tSIK3
VDD = 2.7 to 5.5 V
150
ns
(to SCK
↑)
500
ns
SB0, 1 hold time (from SCK
↑) tKSI3
tKCY3/2
ns
SCK
↓ → SB0, 1 output
tKSO3
RL = 1 k
, Note
VDD = 2.7 to 5.5 V
0
250
ns
delay time
CL = 100 pF
0
1000
ns
SCK
↑ → SB0, 1 ↓
tKSB
tKCY3
ns
SB0, 1
↓ → SCK ↓
tSBK
tKCY3
ns
SB0, 1 low-level width
tSBL
tKCY3
ns
SB0, 1 high-level width
tSBH
tKCY3
ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
SBI mode (SCK ... external clock input (slave)): (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY4
VDD = 2.7 to 5.5 V
800
ns
3200
ns
SCK high-/low-level width
tKL4, tKH4
VDD = 2.7 to 5.5 V
400
ns
1600
ns
SB0, 1 setup time
tSIK4
VDD = 2.7 to 5.5 V
100
ns
(to SCK
↑)
150
ns
SB0, 1 hold time (from SCK
↑) tKSI4
tKCY4/2
ns
SCK
↓ → SB0, 1 output
tKSO4
RL = 1 k
, Note
VDD = 2.7 to 5.5 V
0
300
ns
delay time
CL = 100 pF
0
1000
ns
SCK
↑ → SB0, 1 ↓
tKSB
tKCY4
ns
SB0, 1
↓ → SCK ↓
tSBK
tKCY4
ns
SB0, 1 low-level width
tSBL
tKCY4
ns
SB0, 1 high-level width
tSBH
tKCY4
ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
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