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參數(shù)資料
| 型號： | UPD75P336GC-3B9 |
| 廠商： | NEC Corp. |
| 英文描述： | DIODE ZENER SINGLE 500mW 56Vz 2.2mA-Izt 0.05 0.1uA-Ir 39Vr DO35-GLASS 5K/REEL |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 320K |
| 代理商： | UPD75P336GC-3B9 |
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9
μ
PD75P048
1.2 NON-PORT PINS (2/2)
Pin Name
X1, X2
XT1, XT2
RESET
MD0 - MD3
V
PP
Note 2
V
DD
V
SS
Shared
Pin
–
–
–
P30 - P33
–
–
–
When Reset
–
–
–
Input
–
–
–
Input/
Output
Input
Input
Input
I/O
–
–
–
Function
Crystal/ceramic resonator connection for main
system clock generation. When external clock
signal is used, it is applied to X1, and its
reverse phase signal is applied to X2.
Crystal connection for subsystem clock
generation. When external clock signal is
used, it is applied to XT1, and its reverse
phase signal is applied to XT2. XT1 can be
used as a 1-bit input (test).
System reset input
Operation mode selection pins during the
PROM write/verify cycles.
Normally connected to V
DD
directly; +12.5 V is
applied as the programming voltage during the
PROM write/verify cycles.
Positive power supply
GND potential
I/O Circuit
Type
Note 1
–
–
E-B
–
–
–
B
Note 1.
The circle (
2.
The V
PP
should be connected to V
DD
directly in normal operation mode. If V
PP
and V
DD
pins are not
connected, the
μ
PD75P048 does not operate correctly.
) indicates the Schmitt trigger input.
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