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參數(shù)資料
| 型號(hào)： | UPD75P54G |
| 廠商： | NEC Corp. |
| 英文描述： | 4-Bit, Single-Chip, One-Time Programmable (OTP) CMOS Microcomputers With Serial I/O |
| 中文描述： | 4位，單芯片，一次性可編程（OTP）的CMOS單片機(jī)串行I /輸出 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大小： | 320K |
| 代理商： | UPD75P54G |
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23
μ
PD75P048
AC CHARACTERISTICS
(T
a
= -10 to +70
°
C, V
DD
= 2.7 to 6.0 V)
Parameter
Symbol
t
CY
Conditions
MIN.
0.95
3.8
TYP.
MAX.
32
32
Unit
μ
s
μ
s
CPU Clock Cycle Time
(Minimum Instruction
Execution Time
= 1 Machine Cycle)
Note 1
w/main system clock
V
DD
= 4.5 to 6.0V
w/subsystem clock
114
122
125
μ
s
TI0 Input Frequency
f
TI
V
DD
= 4.5 to 6.0 V
0
0
1
MHz
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
275
TI0 Input High-, Low-
Level Widths
t
TIH
,
t
TIL
V
DD
= 4.5 to 6.0 V
0.48
1.8
Interrupt Input High-,
Low-Level Widths
t
INTH
,
t
INTL
INT0
INT1, 2, 4
KR0-7
Note 2
10
10
10
RESET Low-Level Width
t
RSL
Note 1.
The CPU clock (
Φ
) cycle time is de-
termined by the oscillation frequency
of the connected oscillator, system
clock control register (SCC), and
processor clock control register (PCC).
The figure on the right is cycle time t
CY
vs. supply voltage V
DD
characteristics
at the main system clock.
2.
2
tCY
or 128/f
X
depending on the set-
ting of the interrupt mode register
(IM0).
0
1
2
3
4
5
6
0.5
1
2
3
4
5
6
32
Supply voltage V
DD
[V]
C
C
t
CY
vs V
DD
(with main system clock)
Operation
quaranteed
range
μ
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