參數(shù)資料
型號(hào)： UPD75P64G
廠商： NEC Corp.
英文描述： 4-Bit, Single-Chip, One-Time Programmable (OTP) CMOS Microcomputers With Serial I/O
中文描述： 4位，單芯片，一次性可編程（OTP）的CMOS單片機(jī)串行I /輸出
文件頁(yè)數(shù)： 30/40頁(yè)
文件大?。?/td> 320K
代理商： UPD75P64G
30
μ
PD75P048
EEPROM CHARACTERISTICS
Parameter
Symbol
I
DD7
Conditions
MIN.
TYP.
6.5
2
MAX.
20
6
Unit
mA
mA
Supply current for
EEPROM access
Note 1
4.19MHz crystal oscillator V
DD
= 5V+10%
Note 2
C1 = C = 22pF
V
DD
= 3V+10%
Note 3
Note 1.
Current flowing through the internal pull-up resistor is not included.
2.
When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used.
3.
When PCC is set to 0000 and the low-speed mode is used.
EEPROM WRITE TIME
Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock
as follows:
Oscillation Frequency of Main
System Clock (f
X
)
Setting of EEPROM Control Register
EWTC1
0
0
1
Write time
EWTC0
0
1
0
f
X
= 2.0 to 5.0 MHz
f
X
= 2.0 to 4.2 MHz
f
X
= 2.0 MHz
2
12
x 18/f
X
(17.6 ms)
2
11
x 18/f
X
(8.8 ms)
2
10
x 18/f
X
Remarks
( ): f
X
= 4.19 MHz
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a
= –10 to +70
°
C)
Parameter
Symbol
V
DDDR
Conditions
MIN.
TYP.
MAX.
Unit
Data Retention Supply
Voltage
2.0
6.0
V
I
DDDR
V
DDDR
= 2.0 V
0.1
10
μ
A
Release Signal Set Time
t
SREL
t
WAIT
0
μ
s
ms
ms
Released by RESET
Released by interrupt request
2
17
/f
X
Note 1.
Does not include current flowing through internal pull-up resistor
2.
The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable
operation when oscillation is started.
3.
Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
–
–
–
–
BTM2
0
0
1
1
BTM1
0
1
0
1
BTM0
0
1
1
1
WAIT time ( ): f
X
= 4.19 MHz
2
20
/f
X
(approx. 250 ms)
2
17
/f
X
(approx. 31.3 ms)
2
15
/f
X
(approx. 7.82 ms)
2
13
/f
X
(approx. 1.95 ms)
Oscillation Stabilization
Wait Time
Note 2
Data Retention Supply
Current
Note 1
Note 3
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