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參數(shù)資料
| 型號(hào)： | UPD77210 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 18/74頁(yè) |
| 文件大?。?/td> | 467K |
| 代理商： | UPD77210 |
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Data Sheet U15203EJ3V0DS
18
μ
PD77210, 77213
Host interface
Pin No.
Pin Name
144-pin LQFP
161-pin FBGA
I/O
Function
Alternate
Pin
HA1
63
J3
Input
Host address 1
This pin specifies a register that is accessed by the
host interface pins (HD7 to HD0, or HD15 to HD0).
1: The host interface status register (HST) is
accessed.
0: The host transmit data register (HDT (out)) is
accessed for read (HRD = 0) and the host receive
data register (HDT (in)) is accessed for write (HWR
= 0).
HA0
62
K1
Input
Host address 0
This pin specifies a register that is accessed by HD7
to HD0 in 8-bit mode. This pin is invalid in 16-bit
mode.
1: Bits 15 to 8 of HST, HDT (in), and HDT (out) are
accessed.
0: Bits 7 to 0 of HST, HDT (in), and HDT (out)
are accessed.
HCS
61
J2
Input
Chip select input
HRD
64
K2
Input
Host read input
HWR
66
J4
Input
Host write input
HRE
65
L2
Output
Host read enable output
HWE
67
L1
Output
Host write enable output
HD0 to
HD7
49 to 56
F4,F2,F3,G1,
G3,G2,H3,H2
I/O
(3S)
8-bit host data bus
These pins constitute a host data bus in 8-bit host
mode. Access to 16-bit data for input/output is
controlled by the HA0 pin, and the data is accessed
two times such that it is divided into two blocks of 8-
bit data.
In 16-bit mode, the lower 8 bits of the data are
input/output.
HD8 to
HD15
39 to 46
C2,C3,D1,D2,
D3,E3,E1,E2
I/O
(3S)
Host data bus
These pins constitute a host data bus in 16-bit host
mode. They input/output 16-bit data with HD0 to
HD7.
P8 to P15/
INT02,
INT12,
INT22,
INT32,
INT03,
INT13,
INT23,
INT33
Remark
Those pins marked “3S” in the above table enter the high-impedance state while the host interface is not
being accessed.
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