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參數(shù)資料
| 型號： | UPD77210F1-DA2 |
| 廠商： | NEC Corp. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 16位定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 28/74頁 |
| 文件大小： | 467K |
| 代理商： | UPD77210F1-DA2 |
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Data Sheet U15203EJ3V0DS
28
μ
PD77210, 77213
4. RESET FUNCTION
The device is initialized when a low level of the specified width is input to the RESET pin.
4.1 Hardware Reset
The internal circuitry of the
μ
PD77210 Family is initialized when the RESET pin is asserted active (low level) for a
specific period. When the RESET pin is then deasserted inactive (high level), booting of the instruction RAM is
performed in accordance with the status of the port pins (P0, P1, P2, and P3), and then processing is executed
starting from the instruction at address 0x200 (reset entry) of the instruction memory.
5. FUNCTION OF BOOT-UP ROM
The instruction RAM is booted up by using the internal boot-up ROM when power is applied or when the contents
of the instruction memory are to be rewritten by the program.
5.1 Boot at Reset
Immediately after release of a hardware reset, the boot program first reads general-purpose I/O port pins P0 to
P3, and a boot mode (memory boot/host boot/serial boot) is determined by the bit patterns of these port pins. Once
the booting processing has been completed, processing is executed starting from the instruction at address 0x200
(reset entry) of the instruction memory.
P2
P1
P0
Boot Mode
0
0
0
Non-boot
Note
0
0
1
X memory initial boot
0
1
0
Y memory initial boot
0
1
1
XY memory initial boot
1
0
0
External memory initial boot
1
0
1
Host boot
1
1
0
Serial boot
Note
This setting is used when the
μ
PD77210 Family must be reset upon restoration from standby mode after a
reset boot has been executed once.
P3
PLL lock range
0
120 to 160 MHz
1
80 to 120 MHz
5.1.1 Memory boot
The instruction code stored in data memory is transferred to the instruction RAM. Depending on the data memory
from which the instruction code is to be transferred, X memory boot (booting from the X data memory), Y memory
boot (booting from the Y data memory), XY memory boot (booting from the X and Y data memories), or external
memory boot (booting from the external data memory space) may be performed.
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