參數(shù)資料
型號(hào)： UPD780024AGC-xxx-8BS
廠商： NEC Corp.
元件分類： 8位微控制器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 66/96頁(yè)
文件大小： 661K
代理商： UPD780024AGC-XXX-8BS
66
μ
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
(3/3)
(2) Read/Write Operation (T
A
=
–
40 to +85
°
C, V
DD
= 1.8 to 2.7 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.3t
CY
ns
Address setup time
t
ADS
120
ns
Address hold time
t
ADH
20
ns
Input time from address to data
t
ADD1
(2 + 2n)t
CY
–
233
ns
t
ADD2
(3 + 2n)t
CY
–
240
ns
Output time from RD
↓
to address
t
RDAD
0
400
ns
Input time from RD
↓
to data
t
RDD1
(2 + 2n)t
CY
–
325
ns
t
RDD2
(3 + 2n)t
CY
–
332
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.5 + 2n)t
CY
–
92
ns
t
RDL2
(2.5 + 2n)t
CY
–
92
ns
Input time from RD
↓
to WAIT
↓
t
RDWT1
t
CY
–
350
ns
t
RDWT2
t
CY
–
132
ns
Input time from WR
↓
to WAIT
↓
t
WRWT
t
CY
–
100
ns
WAIT low-level width
t
WTL
(0.5 + 2n)t
CY
+ 10
(2 + 2n)t
CY
ns
Write data setup time
t
WDS
60
ns
Write data hold time
t
WDH
20
ns
WR low-level width
t
WRL1
(1.5 + 2n)t
CY
–
60
ns
Delay time from ASTB
↓
to RD
↓
t
ASTRD
20
ns
Delay time from ASTB
↓
to WR
↓
t
ASTWR
2t
CY
–
60
ns
Delay time from
t
RDAST
0.8t
CY
–
60
1.2t
CY
ns
RD
↑
to ASTB
↑
at external fetch
Hold time from
t
RDADH
0.8t
CY
–
60
1.2t
CY
+ 120
ns
RD
↑
to address at external fetch
Write data output time from RD
↑
t
RDWD
40
ns
Write data output time from WR
↓
t
WRWD
40
240
ns
Hold time from WR
↑
to address
t
WRADH
0.8t
CY
–
60
1.2t
CY
+ 120
ns
Delay time from WAIT
↑
to RD
↑
t
WTRD
0.5t
CY
2.5t
CY
+ 100
ns
Delay time from WAIT
↑
to WR
↑
t
WTWR
0.5t
CY
2.5t
CY
+ 100
ns
Caution
T
CY
can only be used when the MIN. value is 1.6
μ
s.
Remarks
1.
2.
3.
t
CY
= T
CY
/4
n indicates the number of waits.
C
L
= 100 pF (C
L
indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
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