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| 型號(hào)： | UPD78053GC-XXX-8BT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 159/237頁(yè) |
| 文件大?。?/td> | 2394K |
| 代理商： | UPD78053GC-XXX-8BT |
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26
LIST OF FIGURES (2/8)
Figure No.
Title
Page
6-18.
P130 and P131 Block Diagram .....................................................................................................
149
6-19.
Port Mode Register Format ...........................................................................................................
152
6-20.
Pull-Up Resistor Option Register Format ......................................................................................
153
6-21.
Memory Expansion Mode Register Format ...................................................................................
154
6-22.
Key Return Mode Register Format ................................................................................................
155
7-1.
Block Diagram of Clock Generator ................................................................................................
160
7-2.
Subsystem Clock Feedback Resistor ............................................................................................
161
7-3.
Processor Clock Control Register Format .....................................................................................
162
7-4.
Oscillation Mode Selection Register Format .................................................................................
164
7-5.
Main System Clock when Writing to OSMS ..................................................................................
164
7-6.
External Circuit of Main System Clock Oscillator ..........................................................................
165
7-7.
External Circuit of Subsystem Clock Oscillator .............................................................................
166
7-8.
Examples of Incorrect Oscillator Connection ................................................................................
166
7-9.
Main System Clock Stop Function ................................................................................................
170
7-10.
System Clock and CPU Clock Switching ......................................................................................
173
8-1.
16-Bit Timer/Event Counter Block Diagram ...................................................................................
179
8-2.
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ...............................................
180
8-3.
Timer Clock Selection Register 0 Format ......................................................................................
183
8-4.
16-Bit Timer Mode Control Register Format ..................................................................................
185
8-5.
Capture/Compare Control Register 0 Format ...............................................................................
186
8-6.
16-Bit Timer Output Control Register Format ................................................................................
187
8-7.
Port Mode Register 3 Format ........................................................................................................
188
8-8.
External Interrupt Mode Register 0 Format ...................................................................................
189
8-9.
Sampling Clock Select Register Format ........................................................................................
190
8-10.
Control Register Settings for Interval Timer Operation ..................................................................
191
8-11.
Interval Timer Configuration Diagram ............................................................................................
192
8-12.
Interval Timer Operation Timings ..................................................................................................
192
8-13.
Control Register Settings for PWM Output Operation ...................................................................
194
8-14.
Example of D/A Converter Configuration with PWM Output .........................................................
195
8-15.
TV Tuner Application Circuit Example ...........................................................................................
195
8-16.
Control Register Settings for PPG Output Operation ....................................................................
196
8-17.
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
One Capture Register ...................................................................................................................
197
8-18.
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................
198
8-19.
Timing of Pulse Width Measurement Operation by Free-Running Counter and
One Capture Register (with Both Edges Specified) ......................................................................
198
8-20.
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ........
199
8-21.
Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) ..........................................................................................................
200
8-22.
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ..................................................................................................................
201
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