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參數(shù)資料
| 型號： | UPD784215AY |
| 廠商： | NEC Corp. |
| 英文描述： | 16-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 16位單晶片微控制器 |
| 文件頁數(shù)： | 52/100頁 |
| 文件大?。?/td> | 561K |
| 代理商： | UPD784215AY |
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Data Sheet U14121EJ2V0DS00
52
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
8. INTERRUPT FUNCTIONS
The three types of interrupt request servicing shown in Table 8-1 can be selected by program.
Table 8-1. Servicing of Interrupt Request
Servicing Mode
Entity of Servicing
Servicing
Contents of PC and PSW
Vectored interrupt
Branches and executes servicing routine
(servicing is arbitrary)
Saves to and restores from
stack
Context switching
Software
Automatically switches register bank,
branches and executes servicing routine
(servicing is arbitrary)
Saves to or restores from
fixed area in register bank
Macro service
Firmware
Executes data transfer between memory
and I/O (servicing is fixed)
Retained
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 29 types of sources,
execution of the BRK instruction, BRKCS instruction, or an operand error.
The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt
servicing and so that which of the two or more interrupts that simultaneously occur should be serviced first can be
determined. When the macro service function is used, however, nesting always proceeds.
The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having
the same priority, are simultaneously generated (refer to
Table 8-2
).
Table 8-2. Interrupt Sources (1/2)
Source
Type
Default
Priority
Name
Trigger
Internal/
External
Macro
Service
BRK instruction
Instruction execution
BRKCS instruction
Instruction execution
Software
Operand error
If result of exclusive OR between operands byte
and byte is not FFH when “MOV STBC, #byte”
instruction, “MOV WDM, #byte” instruction, or
LOCATION instruction is executed
NMI
Pin input edge detection
External
Non-maskable
INTWDT
Overflow of watchdog timer
Internal
0 (highest)
INTWDTM
Overflow of watchdog timer
Internal
1
INTP0
2
INTP1
3
INTP2
4
INTP3
5
INTP4
6
INTP5
7
INTP6
Pin input edge detection
External
INTIIC0
End of I
2
C bus transfer by CSI0
8
INTCSI0
End of 3-wire transfer by CSI0
Maskable
9
INTSER1
Occurrence of UART reception error in ASI1
Internal
√
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