參數(shù)資料
型號： UPD784216AYGC
廠商： NEC Corp.
英文描述： 16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16位單晶片微控制器
文件頁數(shù)： 76/100頁
文件大小： 561K
代理商： UPD784216AYGC
Data Sheet U14121EJ2V0DS00
76
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
AC Characteristics
(1) Read/write operation (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 5.0 V
±
10%
0.5T
2
ns
V
DD
= 3.0 V
±
10%
0.5T
12
ns
Address active time from RD
↑
t
DRA
V
DD
= 2.0 V
±
10%
0.5T
35
ns
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
Delay time from RD
↑
to ASTB
↑
t
DRST
V
DD
= 2.0 V
±
10%
0.5T
40
ns
V
DD
= 5.0 V
±
10%
(1.5
+
n)T
25
ns
V
DD
= 3.0 V
±
10%
(1.5
+
n)T
30
ns
RD low-level width
t
WRL
V
DD
= 2.0 V
±
10%
(1.5
+
n)T
25
ns
V
DD
= 5.0 V
±
10%
(1
+
a)T
24
ns
V
DD
= 3.0 V
±
10%
(1
+
a)T
34
ns
Delay time from address to WR
↓
t
DAW
V
DD
= 2.0 V
±
10%
(1
+
a)T
70
ns
V
DD
= 5.0 V
±
10%
0.5T
14
ns
V
DD
= 3.0 V
±
10%
0.5T
14
ns
Address hold time (from WR
↑
)
t
HRD
V
DD
= 2.0 V
±
10%
0.5T
14
ns
V
DD
= 5.0 V
±
10%
0.5T
+
15
ns
V
DD
= 3.0 V
±
10%
0.5T
+
30
ns
Delay time from ASTB
↓
to data
output
t
DSTOD
V
DD
= 2.0 V
±
10%
0.5T
+
240
ns
V
DD
= 5.0 V
±
10%
0.5T
30
ns
V
DD
= 3.0 V
±
10%
0.5T
30
ns
Delay time from WR
↓
to data
output
t
DWOD
V
DD
= 2.0 V
±
10%
0.5T
30
ns
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
Delay time from ASTB
↓
to WR
↓
t
DSTW
V
DD
= 2.0 V
±
10%
0.5T
20
ns
V
DD
= 5.0 V
±
10%
(1.5
+
n)T
20
ns
V
DD
= 3.0 V
±
10%
(1.5
+
n)T
25
ns
Data setup time (to WR
↑
)
t
SODWR
V
DD
= 2.0 V
±
10%
(1.5
+
n)T
70
ns
V
DD
= 5.0 V
±
10%
0.5T
14
ns
V
DD
= 3.0 V
±
10%
0.5T
14
ns
Data hold time (from WR
↑
)
t
HWOD
V
DD
= 2.0 V
±
10%
0.5T
50
ns
V
DD
= 5.0 V
±
10%
0.5T
9
ns
V
DD
= 3.0 V
±
10%
0.5T
9
ns
Delay time from WR
↑
to ASTB
↑
t
DWST
V
DD
= 2.0 V
±
10%
0.5T
30
ns
V
DD
= 5.0 V
±
10%
(1.5
+
n)T
25
ns
V
DD
= 3.0 V
±
10%
(1.5
+
n)T
30
ns
WR low-level width
t
WWL
V
DD
= 2.0 V
±
10%
(1.5
+
n)T
30
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
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