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8
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
2. MAJOR DIFFERENCES BETWEEN
μ
PD784216Y SUBSERIES AND
μ
PD780058Y SUBSERIES
Series Name
μ
PD784225, 784225Y
Subseries
μ
PD784216Y Subseries
μ
PD780058Y Subseries
Item
CPU
16-bit CPU
8-bit CPU
Minimum
instruction
execution time
With main system
clock selected
160 ns (at 12.5 MHz)
400 ns (at 5.0 MHz)
With subsystem
clock
61
μ
s (at 32.768 kHz)
122
μ
s (at 32.768 kHz)
Memory space
1 Mbytes
64 Kbytes
I/O port
Total
67 pins
86 pins
68 pins
CMOS input
8 pins
8 pins
2 pins
CMOS I/O
59 pins
72 pins
62 pins
N-ch open-drain I/O
6 pins
4 pins
Pins with
ancillary
function
Note 1
Pins with pull-up
resistor
57 pins
70 pins
66 pins (flash memory
model: 62 pins)
LED direct drive
output
16 pins
22 pins
12 pins
Medium-voltage pin
6 pins
4 pins
Timer/counter
16-bit timer/event counter
×
1 unit
8-bit timer/event counter
×
4 units
16-bit timer/event counter
×
1 unit
8-bit timer/event counter
×
6 units
16-bit timer/event counter
×
1 unit
8-bit timer/event counter
×
2 units
Serial interface
UART/IOE (3-wire serial I/O)
×
2 channels
CSI (3-wire serial I/O, multi-master supporting I
2
C
bus
Note 2
)
×
1 channel
UART (time-division transfer
function)/IOE (3-wire
serial I/O)
×
2 channels
CSI (3-wire serial I/O,
2-wire serial I/O,
I
2
C bus)
×
1 channel
CSI (3-wire serial I/O
with automatic
transmission/reception
function)
×
1 channel
Interrupt
NMI pin
Provided
None
Macro service
Provided
None
Context switching
Provided
None
Programmable priority
4 levels
2 levels
Standby function
HALT/STOP/IDLE mode
Power-saving mode: HALT/IDLE Mode
HALT/STOP mode
ROM correction
Provided
None
Provided
Package
80-pin plastic QFP
(14
×
14 mm)
80-pin plastic TQFP
(fine pitch) (12
×
12 mm)
100-pin plastic QFP
(fine pitch) (14
×
14 mm)
100-pin plastic QFP
(14
×
20 mm)
80-pin plastic QFP
(14
×
14 mm)
80-pin plastic TQFP
(fine pitch) (12
×
12 mm)
Notes 1.
Pins with ancillary function are included in the I/O pins.
2.
μ
PD784225Y and 784216Y Subseries only