User’s Manual U17854EJ9V0UD
8
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Differences Between Conventional-Specification Products (
μPD78F114x) and Expanded-
Specification Products (
μPD78F114xA)..................................................................................... 17
1.2 Features......................................................................................................................................... 18
1.3 Applications .................................................................................................................................. 19
1.4 Ordering Information.................................................................................................................... 19
1.5 Pin Configuration (Top View) ...................................................................................................... 21
1.6 78K0R/Kx3 Microcontroller Lineup............................................................................................. 24
1.7 Block Diagram .............................................................................................................................. 25
1.8 Outline of Functions..................................................................................................................... 26
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 28
2.1 Pin Function List .......................................................................................................................... 28
2.2 Description of Pin Functions ...................................................................................................... 33
2.2.1 P00 to P06 (port 0) ........................................................................................................................... 33
2.2.2 P10 to P17 (port 1) ........................................................................................................................... 34
2.2.3 P20 to P27 (port 2) ........................................................................................................................... 35
2.2.4 P30, P31 (port 3) .............................................................................................................................. 35
2.2.5 P40 to P43 (port 4) ........................................................................................................................... 36
2.2.6 P50 to P55 (port 5) ........................................................................................................................... 37
2.2.7 P60 to P63 (port 6) ........................................................................................................................... 37
2.2.8 P70 to P77 (port 7) ........................................................................................................................... 37
2.2.9 P120 to P124 (port 12) ..................................................................................................................... 38
2.2.10 P130 (port 13) ................................................................................................................................ 39
2.2.11 P140, P141 (port 14) ...................................................................................................................... 39
2.2.12 AVREF.............................................................................................................................................. 39
2.2.13 AVSS ............................................................................................................................................... 40
2.2.14 RESET ........................................................................................................................................... 40
2.2.15 REGC............................................................................................................................................. 40
2.2.16 VDD, EVDD ....................................................................................................................................... 40
2.2.17 VSS, EVSS........................................................................................................................................ 40
2.2.18 FLMD0 ........................................................................................................................................... 41
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 42
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 46
3.1 Memory Space .............................................................................................................................. 46
3.1.1 Internal program memory space ...................................................................................................... 53
3.1.2 Mirror area........................................................................................................................................ 55
3.1.3 Internal data memory space............................................................................................................. 56
3.1.4 Special function register (SFR) area ................................................................................................ 57
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 57
3.1.6 Data memory addressing ................................................................................................................. 58
3.2 Processor Registers..................................................................................................................... 63