CHAPTER
6
C
L
OC
K
GENERA
TOR
User’s
Manual
U1
7894EJ9V0UD
189
Figure 6-1. Block Diagram of Clock Generator
fIL
XT1/P123
XT2//P124
fSUB
fCLK
CSS
CLS
fMAIN
fMAINC
OSTS1 OSTS0
OSTS2
3
MOST
18
MOST
17
MOST
15
MOST
13
MOST
11
MSTOP
STOP
EXCLK OSCSEL
AMPH
4
fIH
X1/P121
X2/EXCLK
/P122
fMX
OSCSELS
fX
fEX
fXT
XTSTOP
CLS
HIOSTOP
MCM0
MCS
MD
IV2
MD
IV1
MD
IV0
CPU
fMAIN/2
5
fMAIN/2
4
fMAIN/2
3
fMAIN/2
2
fMAIN/2
fMAIN
1
MOST
10
MOST
9
MOST
8
TAU0
EN
SAU0
EN
SAU1
EN
IIC0
EN
ADC
EN
DAC
EN
RTC
EN
fSUB/2
EXB
EN
External bus interface
Internal bus
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
Oscillation stabilization
time select register (OSTS)
System clock control
register (CKC)
X1 oscillation
stabilization time counter
Oscillation stabilization time counter
status register
(OSTC)
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
Subsystem clock
oscillator
Crystal
oscillation
Clock operation mode
control register
(CMC)
Internal
high-speed
oscillator
(8 MHz (typ.))
Internal
low-speed
oscillator
(240 kHz (typ.))
Clock operation status
control register
(CSC)
Main system
clock source
selection
Watchdog timer
Real-time counter, clock
output/buzzer output
Peripheral enable register 1
(PER1)
Clock output/
buzzer output
Prescaler
Selector
Selection of
CPU clock and
peripheral
hardware clock
source
Controller
Peripheral enable register 0
(PER0)
Timer array unit
Serial array unit 0
Serial array unit 1
Serial interface IIC0
A/D converter
D/A converter
Real-time counter
Standby control
Controller
<R>