參數(shù)資料
型號: UPSD3214AV-24U6T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的
文件頁數(shù): 14/176頁
文件大小: 1081K
代理商: UPSD3214AV-24U6T
μ
PSD323X
14/176
Table 2. 80-Pin Package Pin Description
Port Pin
Signal
Name
Pin No.
In/Out
Function
Basic
Alternate
P0.0
AD0
36
I/O
External Bus
Multiplexed Address/Data bus A1/D1
P0.1
AD1
37
I/O
Multiplexed Address/Data bus A0/D0
P0.2
AD2
38
I/O
Multiplexed Address/Data bus A2/D2
P0.3
AD3
39
I/O
Multiplexed Address/Data bus A3/D3
P0.4
AD4
41
I/O
Multiplexed Address/Data bus A4/D4
P0.5
AD5
43
I/O
Multiplexed Address/Data bus A5/D5
P0.6
AD6
45
I/O
Multiplexed Address/Data bus A6/D6
P0.7
AD7
47
I/O
Multiplexed Address/Data bus A7/D7
P1.0
T2
52
I/O
General I/O port pin
Timer 2 Count input
P1.1
T2EX
54
I/O
General I/O port pin
Timer 2 Trigger input
P1.2
RxD2
56
I/O
General I/O port pin
2nd UART Receive
P1.3
TxD2
58
I/O
General I/O port pin
2nd UART Transmit
P1.4
ADC0
59
I/O
General I/O port pin
ADC Channel 0 input
P1.5
ADC1
60
I/O
General I/O port pin
ADC Channel 1 input
P1.6
ADC2
61
I/O
General I/O port pin
ADC Channel 2 input
P1.7
ADC3
64
I/O
General I/O port pin
ADC Channel 3 input
P2.0
A8
51
I/O
External Bus, Address A8
P2.1
A9
53
I/O
External Bus, Address A9
P2.2
A10
55
I/O
External Bus, Address A10
P2.3
A11
57
I/O
External Bus, Address A11
P3.0
RxD1
75
I/O
General I/O port pin
UART Receive
P3.1
TxD1
77
I/O
General I/O port pin
UART Transmit
P3.2
INTO
79
I/O
General I/O port pin
Interrupt 0 input / timer0 gate
control
P3.3
INT1
2
I/O
General I/O port pin
Interrupt 1 input / timer1 gate
control
P3.4
T0
40
I/O
General I/O port pin
Counter 0 input
P3.5
T1
42
I/O
General I/O port pin
Counter 1 input
P3.6
SDA1
44
I/O
General I/O port pin
I
2
C Bus serial data I/O
P3.7
SCL1
46
I/O
General I/O port pin
I
2
C Bus clock I/O
P4.0
SDA2
33
I/O
General I/O port pin
I
2
C serial data I/O forDDC
interface
P4.1
SCL2
31
I/O
General I/O port pin
I
2
C clock I/O for DDC interface
P4.2
VSYNC
30
I/O
General I/O port pin
VSYNC input for DDC interface
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