參數(shù)資料
型號： uPSD3234BV-24U6T
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 73/170頁
文件大?。?/td> 2717K
代理商： UPSD3234BV-24U6T
73/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Serial Status Register (SxSTA: S1STA, S2STA)
SxSTA is a “Read-only” register. The contents of
this register may be used as a vector to a service
routine. This optimized the response time of the
software and consequently that of the I
2
C-bus.
The status codes for all possible modes of the I
2
C-
bus interface are given Table
54
.
This flag is set, and an interrupt is generated, after
any of the following events occur.
1.
Own slave address has been received during
AA = 1: ack_int
2.
The general call address has been received
while GC(SxADR.0) = 1 and AA = 1:
3.
A data byte has been received or transmitted
in Master Mode (even if arbitration is lost):
ack_int
A data byte has been received or transmitted
as selected slave: ack_int
A stop condition is received as selected slave
receiver or transmitter: stop_int
Data Shift Register (SxDAT: S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted
or data which has just been received. The MSB
(Bit 7) is transmitted or received first; that is, data
shifted from right to left.
4.
5.
Table 53. Serial Status Register (SxSTA)
Table 54. Description of the SxSTA Bits
Note: 1. Interrupt Flag Bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register.
2. I
C Interrupt Flag (INTR) can occur in below case. (except DDC2B Mode at SWENB=0)
Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT)
7
6
5
4
3
2
1
0
GC
STOP
INTR
TX_MODE
BBUSY
BLOST
/ACK_REP
SLV
Bit
Symbol
Function
7
GC
General Call Flag
6
STOP
Stop Flag. This bit is set when a STOP condition is received
5
INTR
(1,2)
Interrupt Flag. This bit is set when an I2C Interrupt condition is requested
4
TX_MODE
Transmission Mode Flag.
This bit is set when the I2C is a transmitter; otherwise this bit is reset
3
BBUSY
Bus Busy Flag.
This bit is set when the bus is being used by another master; otherwise, this bit is reset
2
BLOST
Bus Lost Flag.
This bit is set when the master loses the bus contention; otherwise this bit is reset
1
/ACK_REP
Acknowledge Response Flag.
This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal
0
SLV
Slave Mode Flag.
This bit is set when the I2C plays role in the Slave Mode; otherwise this bit is reset
7
6
5
4
3
2
1
0
SxDAT7
SxDAT6
SxDAT5
SxDAT4
SxDAT3
SxDAT2
SxDAT1
SxDAT0
相關(guān)PDF資料
PDF描述
uPSD3234BV-40U1T Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3234BV-40U6T Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3234 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3251(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
uPSD3251 Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
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參數(shù)描述
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