參數(shù)資料
型號： uPSD3251
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的Flash可編程系統(tǒng)設(shè)備)
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核（帶8032微控制器內(nèi)核的閃存可編程系統(tǒng)設(shè)備）
文件頁數(shù)： 42/128頁
文件大?。?/td> 1566K
代理商： UPSD3251
μPSD3251F
42/128
The following SFR registers (Tables 29 and 30)
are used to control the mapping of alternate func-
tions onto the I/O port bits. Port 1 alternate func-
tions are controlled using the P1SFS register,
except for Timer 2 and the 2nd UART which are
enabled by their configuration registers. P1.0 to
P1.3 are default to GPIO after reset.
Port 3 pins 6 and 7 have been modified from the
standard 8032. These pins that were used for
READ and WRITE control signals are now GPIO
or I
2
C bus pins. The READ and WRITE pins are
assigned to dedicated pins.
Port 3 (I
2
C) alternate functions are controlled us-
ing the P3SFS Special Function Selection regis-
ter. After a reset, the I/O pins default to GPIO. The
alternate function is enabled if the corresponding
bit in the P3SFS register is set to '1.' Other Port 3
alternative functions (UART, Interrupt, and Timer/
Counter) are enabled by their configuration regis-
ter and do not require setting of the bits in P3SFS.
Table 29. P1SFS (91H)
Table 30. P3SFS (93H)
7
6
5
4
3
2
1
0
0=Port 1.7
1=ACH3
0=Port 1.6
1=ACH2
0=Port 1.5
1=ACH1
0=Port 1.4
1=ACH0
Bits Reserved
Bits Reserved
7
6
5
4
3
2
1
0
0 = Port 3.7
1 = SCL
from I
2
C unit
0 = Port 3.6
1 = SDA
from I
2
C unit
Bits are reserved.
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參數(shù)描述
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