參數(shù)資料
型號(hào)： UPSD3254B-24T1
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 61/176頁
文件大小： 1214K
代理商： UPSD3254B-24T1
61/176
μPSD325X DEVICES
Table 44. Description of the SCON Bits
Bit
Symbol
Function
7
SM0
(SM1,SM0)=(0,0): Shift Register. Baud rate = f
OSC
/12
(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f
OSC
/64 or f
OSC
/32
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable
6
SM1
5
SM2
Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if
SM2 is set to ’1,’ R1 will not be activated if its received 8th data bit (RB8) is ’0.’ In Mode
1, if SM2=1, R1 will not be activated if a valid Stop Bit was not received. In Mode 0, SM2
should be ’0’
4
REN
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception
3
TB8
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired
2
RB8
In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used
1
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the
beginning of the Stop Bit in the other modes, in any serial transmission. Must be cleared
by software
0
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the Stop Bit in the other modes, in any serial reception (except for
SM2). Must be cleared by software
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