參數(shù)資料
型號(hào)： UPSD3254B-40T6T
廠商： 意法半導(dǎo)體
英文描述： Two and Three Channel Codewheels
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 140/176頁
文件大?。?/td> 1214K
代理商： UPSD3254B-40T6T
μPSD325X DEVICES
140/176
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD MODULE requires a Re-
set (RESET) pulse of duration t
NLNH-PO
after V
CC
is steady. During this period, the device loads in-
ternal configurations, clears some of the registers
and sets the Flash memory into operating mode.
After the rising edge of Reset (RESET), the PSD
MODULE remains in the Reset Mode for an addi-
tional period, t
OPR
, before the first memory access
is allowed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, WRITE
Strobe (WR, CNTL0) High, during Power-on
RESET for maximum security of the data contents
and to remove the possibility of a byte being writ-
ten on the first edge of WRITE Strobe (WR). Any
Flash memory WRITE cycle initiation is prevented
automatically when V
CC
is below V
LKO
.
Warm RESET
Once the device is up and running, the PSD MOD-
ULE can be reset with a pulse of a much shorter
duration, t
NLNH
. The same t
OPR
period is needed
before the device is operational after a Warm
RESET. Figure 71 shows the timing of the Power-
up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 105 shows the I/O pin, register and PLD sta-
tus during Power-on RESET, Warm RESET, and
Power-down Mode. PLD outputs are always valid
during Warm RESET, and they are valid in Power-
on RESET once the internal Configuration bits are
loaded. This loading is completed typically long
before the V
CC
ramps up to operating level. Once
the PLD is active, the state of the outputs are de-
termined by the PLD equations.
Reset of Flash Memory Erase and Program
Cycles
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the READ Mode within a period of t
NLNH-A
.
Figure 71. Reset (RESET) Timing
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
相關(guān)PDF資料
PDF描述
UPSD3254B-40U1 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
UPSD3254B-40U1T Two and Three Channel Codewheels
UPSD3254B-40U6 Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
UPSD3254B-40U6T Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
UPSD3254BV-40T1 POWERLINE: RP30-S_DE - 2:1 Wide Input Voltage Range- 30 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- International Safety Standard Approvals- Ul 1950 Component Recognised- Standard 50.8 x40.6x10.2mm Package- Efficiency to 90%
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3254B-40U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3254B-40U1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3254B-40U6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3254B-40U6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3254BV 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
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