參數(shù)資料
型號： UPSD3254B-40U1
廠商： 意法半導(dǎo)體
元件分類： 8位微控制器
英文描述： 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述： 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù)： 16/176頁
文件大?。?/td> 1214K
代理商： UPSD3254B-40U1
μPSD325X DEVICES
16/176
52 PIN PACKAGE I/O PORT
The 52-pin package members of the μPSD325X
devices have the same port pins as those of the
80-pin package except:
I
Port 0 (P0.0-P0.7, external address/data bus
AD0-AD7)
I
Port 2 (P2.0-P2.3, external address bus A8-
A11)
I
Port A (PA0-PA7)
I
Port D (PD2)
I
Bus control signal (RD,WR,PSEN,ALE)
Pin 5 requires a pull-up resistor (2k
for 3V de-
vices, 7.5k
for 5V devices) for all devices, with
or without USB function.
PB0
80
I/O
General I/O port pin
1. PLD Macro-cell outputs
2. PLD inputs
3. Latched Address Out (A0-A7)
PB1
78
I/O
General I/O port pin
PB2
76
I/O
General I/O port pin
PB3
74
I/O
General I/O port pin
PB4
73
I/O
General I/O port pin
PB5
72
I/O
General I/O port pin
PB6
67
I/O
General I/O port pin
PB7
66
I/O
General I/O port pin
PC0
TMS
20
I
JTAG pin
1. PLD Macro-cell outputs
2. PLD inputs
3. SRAM stand by voltage input
(V
STBY
)
4. SRAM battery-on indicator
(PC4)
5. JTAG pins are dedicated pins
PC1
TCK
16
I
JTAG pin
PC2
V
STBY
15
I/O
General I/O port pin
PC3
TSTAT
14
I/O
General I/O port pin
PC4
TERR
9
I/O
General I/O port pin
PC5
TDI
7
I
JTAG pin
PC6
TDO
6
O
JTAG pin
PC7
5
I/O
General I/O port pin
PD1
CLKIN
3
I/O
General I/O port pin
1. PLD I/O
2. Clock input to PLD and APD
PD2
CSI
1
I/O
General I/O port pin
1. PLD I/O
2. Chip select to PSD Module
Vcc
12
Vcc
50
GND
13
GND
29
GND
69
NC
11
NC
17
NC
71
Port Pin
Signal
Name
Pin No.
In/Out
Function
Basic
Alternate
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參數(shù)描述
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