參數(shù)資料
型號: UPSD3254B-40U6
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù): 134/176頁
文件大?。?/td> 1214K
代理商: UPSD3254B-40U6
μPSD325X DEVICES
134/176
Port D – Functionality and Structure
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). See Figure 67 and Figure 68.
This port does not support Address Out Mode, and
therefore no Control Register is required. Of the
eight bits in the Port D registers, only Bits 2 and 1
are used to configure pins PD2 and PD1.
Port D can be configured to perform one or more
of the following functions:
I
MCU I/O Mode
I
CPLD Output – External Chip Select (ECS1-
ECS2)
I
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
I
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
I
CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
I
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Figure 67. Port D Structure
M
DATA OUT
REG.
D
Q
D
Q
WR
WR
ECS[2:1]
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI06606
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