參數(shù)資料
型號： UPSD3254BV-40T1T
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 139/176頁
文件大小： 1214K
代理商： UPSD3254BV-40T1T
139/176
μPSD325X DEVICES
Table 103. Power Management Mode Registers PMMR2
1
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 104. APD Counter Operation
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD Array
WR
0 = on WR input to the PLD AND Array is connected.
1 = off WR input to PLD AND Array is disconnected, saving power.
Bit 3
PLD Array
RD
0 = on RD input to the PLD AND Array is connected.
1 = off RD input to PLD AND Array is disconnected, saving power.
Bit 4
PLD Array
PSEN
0 = on PSEN input to the PLD AND Array is connected.
1 = off PSEN input to PLD AND Array is disconnected, saving power.
Bit 5
PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
APD Enable Bit
ALE Level
APD Counter
0
X
Not Counting
1
Pulsing
Not Counting
1
0 or 1
Counting (Generates PDN after 15 Clocks)
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