參數(shù)資料
型號(hào)： UPSD3432E-40U6T
廠(chǎng)商： 意法半導(dǎo)體
英文描述： Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
中文描述： Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器
文件頁(yè)數(shù)： 210/264頁(yè)
文件大小： 4320K
代理商： UPSD3432E-40U6T
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uPSD34xx - PSD MODULE
210/264
JTAG ISP Mode.
Four of the pins on Port C are
based on the IEEE 1149.1 JTAG specification and
are used for In-System Programming (ISP) of the
PSD Module and debugging of the 8032 MCU
Module. These pins (TDI, TDO, TMS, TCK) are
dedicated to JTAG and cannot be used for any
other I/O function. There are two optional pins on
Port C (TSTAT and TERR) that can be used to re-
duce programming time during ISP. See
JTAG
ISP and JTAG Debug, page 226
.
Other Port Capabilities.
It is possible to change
the type of output drive on the ports at run-time. It
is also possible to read the state of the output en-
able signal of the output driver at run-time. The fol-
lowing sections provide the details.
Port Pin Drive Options.
The csiop Drive Select
registers allow reconfiguration of the output drive
type for certain pins on Ports A, B, C, and D. The
8032 can change the default drive type setting at
run-time. The is no action needed in PSDsoft Ex-
press to change or define these pin output drive
types.
Figure 80., page 200
shows the csiop Drive
Select register output controlling the pin output
driver. The default setting for drive type for all pins
on Ports A, B, C, and D is a standard CMOS push-
pull output driver.
Note:
When a pin on Port A, B, C, D is not used as
an output and has no external device driving it as
an input (floating pin), excess power consumption
can be avoided by placing a weak pull-up resistor
(100K
) to V
DD
which keeps the CMOS input pin
from floating.
Drive Select Registers.
The csiop Drive Select
Registers will configure a pin output driver as
Open Drain or CMOS push/pull for some port pins,
and controls the slew rate for other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain, and the resistor should
be sized not to exceed the current sink capability
of the pin (see DC specifications). Open Drain out-
puts are diode clamped, thus the maximum volt-
age on an pin configured as Open Drain is V
DD
+
0.7V.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to
logic '1.'
Note:
The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to '1.' The default rate is standard slew
rate (see AC specifications).
Table
136
through
Table 139., page 211
show the
csiop Drive Registers for Ports A, B, C, and D. The
tables summarize which pins can be configured as
Open Drain outputs and which pins the slew rate
can be changed. The default output type is CMOS
push/pull output with normal slew rate.
Enable Out Registers.
The state of the output
enable signal for the output driver at each pin on
Ports A, B, C, and D can be read at any time by the
8032 when it reads the csiop Enable Output regis-
ters. Logic '1' means the driver is in output mode,
logic ’0’ means the output driver is in high-imped-
ance mode, making the pin suitable for input mode
(read by the input buffer shown in
Figure
80., page 200
). Figure
80
shows the three sources
that can control the pin output enable signal: a
product term from AND-OR array; the csiop Direc-
tion register; or the Peripheral I/O Mode logic (Port
A only). The csiop Enable Out registers represent
the state of the final output enable signal for each
port pin driver, and are defined in
Table
140., page 211
through
Table 143., page 211
.
Table 136. Port A Pin Drive Select Register
(1)
(address = csiop + offset 08h)
Note: 1. Port A not available on 52-pin uPSD34xx devices
2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
3. Default state for register is 00h after reset or power-up
Table 137. Port B Pin Drive Select Register (address = csiop + offset 09h)
Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7
Open Drain
PA6
Open Drain
PA5
Open Drain
PA4
Open Drain
PA3
Slew Rate
PA2
Slew Rate
PA1
Slew Rate
PA0
Slew Rate
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PB7
Open Drain
PB6
Open Drain
PB5
Open Drain
PB4
Open Drain
PB3
Slew Rate
PB2
Slew Rate
PB1
Slew Rate
PB0
Slew Rate
相關(guān)PDF資料
PDF描述
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UPSD3424 High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125
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UPSD3433 Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3433E-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433E-40U6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40T6 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40U6 功能描述:8位微控制器 -MCU uPSD34x Turbo Plus Fast Turbo 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EV-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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