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參數(shù)資料
| 型號(hào)： | UT54LVDSC031-UCA |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | UT54LVDSC031-UCA |
1
FEATURES
q >400.0 Mbps (200 MHz) switching rates
q +340mV differential signaling
q 3.3 V power supply
q TTL compatible outputs
q Cold spare all pins
q Ultra low power CMOS technology
q 3.3ns maximum propagation delay
q 0.35ns maximum differential skew
q Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
q Packaging options:
- 16-lead flatpack (dual in-line)
q Standard Microcircuit Drawing 5962-98652
- QML Q and V compliant part
q Compatible with IEEE 1596.3SCI LVDS
q Compatible with ANSI/TIA/EIA 644-1996 LVDS
Standard
INTRODUCTION
The UT54LVDS032LV Q uad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS032LV accepts low voltage (340mV)
differential input signals and translates them to 5V TTL o utput
levels. The receiver supports a three-state function that may be
used to multiplex outputs. The receiver also supports OPEN,
shorted and terminated (100
) input fail-safe. Receiver output
will be HIGH for all fail-safe conditions.
The UT54LVDS032LV and companion quad line driver
UT54LVDS031LV p rovides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD is tied to VSS.
+
R1
-
R
IN1+
R
IN1-
R
IN2+
R
IN2-
R
IN3+
R
IN3-
R
IN4+
R
IN4-
R
OUT1
R
OUT2
R
OUT4
R
OUT3
EN
+
R 2
-
+
R 3
-
+
R 4
-
Standard Products
UT54LVDS032LV Low Voltage Quad Receiver
Data Sheet
January 21, 2002
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
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