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參數(shù)資料
| 型號(hào)： | UT54LVDSC031-UCC |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 78K |
| 代理商： | UT54LVDSC031-UCC |
6
AC SWITCHING CHARACTERISTICS
1, 2, 3
(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C)
Notes:
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in t he same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50, tr and t f (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter.
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPHLD
6
Differential Propagation Delay High to Low
CL = 10pf (figures 4 and 5)
1.0
4.0
ns
t
PLHD
6
Differential Propagation Delay Low to High
CL = 10pf (figures 4 and 5)
1.0
4.0
ns
tSKD
4
Differential Skew (t
PHLD - tPLHD ) (figures 4 and 5)
0
0.35
ns
t
SK1
4
Channel-to-Channel Skew1 (figures 4 and 5)
0
0.5
ns
tSK2
4
Chip-to-Chip Skew
5 (figures 4 and 5)
1.5
ns
tTLH
4
Rise Time (figures 4 and 5)
1.2
ns
tTHL
4
Fall Time (figures 4 and 5)
1.2
ns
t
PHZ
4
Disable Time High to Z (figures 6 and 7)
12
ns
tPLZ
4
Disable Time Low to Z (figures 6 and 7)
12
ns
tPZH
4
Enable Time Z to High (figures 6 and 7)
12
ns
t
PZL
4
Enable Time Z to Low (figures 6 and 7)
12
ns
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