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參數(shù)資料
| 型號： | V23806-A8-C102 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, XFO |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 178K |
| 代理商： | V23806-A8-C102 |
Fiber Optics
V23806-A8-C102, MM 1300 nm LED ATM 10 dB 155 MBd 1x9 Trx, ISO Studs
2
The data rate is scalable and the ATM protocol is the basis of
the broadband public networks being standardized in the Inter-
national Telegraph and Telephone Consultative Committee
(CCITT). ATM can also be used in local private applications.
FDDI is a Dual Token Ring standard developed in the U.S. by the
Accredited National Standards Committee (ANSC) X3T9, within
the Technical Committee X3T9.5. It is applied to the local area
networks of stations, transferring data at 100 Mbits/s with a
125 MBaud transmission rate. LCF FDDI is specially developed
for short distance applications of up to 500 m (fiber-to-the-desk)
as compared to 2 km for backbone applications.
Fast Ethernet was developed because of the higher bandwidth
requirement in local area networking. It is based on the proven
effectiveness of millions of installed Ethernet systems.
The Infineon multimode transceiver is a single unit comprised
of a transmitter, a receiver, and an SC receptacle. This design
frees the customer from many alignment and PC board layout
concerns. The modules are designed for low cost applications.
Notes
1. FDDI Token Ring, Low Cost Fiber Physical Layer Medium Depen-
dent (LCF-PMD) ANSI X3T9.5 / 92 LCF-PMD / Proposed Rev. 1.3,
September 1, 1992. American National Standard.
2. FDDI Token Ring, Physical Layer Medium Dependent (PMD) ANSI
X3.166-1990 American National Standard. ISO/IEC 9314-3: 1990.
Pin Description
TECHNICAL DATA
The electro-optical characteristics described in the following
tables are valid only for use under the recommended operating
conditions.
Recommended Operating Conditions
Notes
1. For V
CC
–V
EE
(min., max.). 50% duty cycle. The supply current
(I
CC2
+I
CC3
) does not include the load drive current (Icc1). Add max.
45 mA for the three outputs. Load is 50
into V
CC
–2V.
2. To maintain good LED reliability, the device should not be held in the
ON state for more than the specified time. Normal operation should
be done with 50% duty cycle.
3. To achieve proper PECL output levels the 50
termination should be
done to V
CC
–2 V. For correct termination see the application notes.
Pin Name
Level/Logic
Pin#
Description
R
x
V
EE
Rx Ground Power Supply 1
Negative power sup-
ply, normally ground
RD
Rx Output
Data
PECL Output
2
Receiver output data
RDn
3
Inverted receiver out-
put data
RxSD
RX Signal
Detect
PECL Output
active high
4
High level on this out-
put shows there is an
optical signal.
R
x
V
CC
Rx +5 V
T
x
V
CC
TxDn
Power Supply 5
Positive power sup-
ply, +5 V
Tx +5 V
6
Tx Input
Data
PECL Input
7
Inverted transmitter
input data
TxD
8
Transmitter input
data
T
x
V
EE
Tx Ground Power Supply 9
Negative power sup-
ply, normally ground
Case
Support
Not Connect-
ed
S1/
S2
Support stud, not
connected
Parameter
Symbol
Min.
Typ.
Max.
Units
°
C
V
Ambient Temperature
T
AMB
V
CC–
V
EE
4.75
I
CC
0
70
Power Supply Voltage
Supply Current +5 V
(1)
Transmitter
5.0
5.25
140
170
210
mA
Data Input
High Voltage
V
IH
–V
CC
–1165
–880
mV
Data Input
Low Voltage
V
IL
–V
CC
–1810
–1475 mV
Input Data Rise/Fall,
20%–80%
Data High Time
(2)
Receiver
t
R
, t
F
0.4
1.3
ns
t
on
1000
Output Current
l
O
t
DCD
25
mA
Input Duty Cycle
Distortion
1.0
ns
Input Data
Dependent Jitter
t
DDj
Input Random Jitter
t
RJ
l
C
0.76
Input Center
Wavelength
Electrical Output Load
(3)
R
L
1260
1380
nm
50
W
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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