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參數(shù)資料
| 型號(hào)： | V23809-E1-E30 |
| 廠商： | SIEMENS A G |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, XFO51 |
| 封裝： | SMT-51 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | V23809-E1-E30 |
V23809-E1-E30, 1300 nm ESCON
Parallel Transceiver
3
Semiconductor Group
Receiver Electro-Optical Characteristics
Receiver
Data Rate
Supply Current
Sensitivity (Average
Power) BOL
Sensitivity (Average
Power) EOL
Saturation
(Average Power)
Signal Detect
Assert Level
Signal Detect
Deassert Level
Signal Detect
Hysteresis
Signal Detect
Reaction Time
Max. Deterministic
Jitter Optical
Input
Max. Random Jitter
RMS Optical
Input
Notes
1. For V
2. Measured at the end of 1 meter fiber and at a duty cycle of 50%.
Cladding modes are removed.
3. P
O
[dBm]=10 log (P
O
/1mW).
4. Measured at BER=1E-12, 200 MBaud transmission rate and 50%
duty cycle 2
-1 PRBS pattern. For 300 MBaud the sensitivity will be
decreased by 4 dB. Center wavelength between 1200 nm and 1500
nm. Fiber type 62.5/125
μ
m/0.29 NA or 50/125
optical rise and fall times 1.2 ns and 1.5 ns (20%–80%) respectively.
5. Over 10
hours lifetime at T
AMB
=35
6. Indicates the presence or absence of optical power at the receiver
input. Signal detect at logic High when asserted. All powers are
average power levels. Pattern 2
-1 at 200 MBaud.
7 Measured at 200 MBaud with Jitter Test Pattern (see page 4). In the
test pattern are five positive and five negative transitions. Measure
the time of the 50% crossing of all 10 transitions. The time of each
crossing is then compared to the mean expected time of the cross-
ing. Deterministic jitter is the range of the timing variations.
8. To convert from specified RMS value to peak-to-peak value (at BER
1E-12), multiply value by 14.
9. Jitter at optical input. Jitter magnitudes above specified level may
increase the bit error rate.
CC
–V
EE
(min., max.). 50% duty cycle.
7
μ
m/0.2 NA. Input
5
°
C.
7
Symbol
Dr
l
CC
P
IN
Min.
100
Typ.
Max.
300
100
–14
Units
MBaud
mA
dBm
(1)
(2, 3, 4)
–32.5
–35.5
(2, 3, 4, 5)
–32
–35
–14
P
SAT
–14
(6)
P
SDA
–44.5
–36
(6)
P
SDD
–45
–37.5
P
P
SDreac
SDA
SDD
–
0.5
1.5
3
dB
3
500
μ
s
(7, 9)
J
D
0.19
% of
Unit
Inter-
vals
(8, 9)
J
R
0.09
Pin Description 10 Bit Interface
Pin#
Pin Name
Level/Logic
Description
1, 6, 9, 26,
43, 45, 48,
51
V
EE
Power
Supply
Ground attached to the
case
2
V
CC
PRE
Preamplifier positive
power supply
3
SIGDET
TTL out
Signal detected
4
LOCKREF
TTL in
Control input for RX PLL
5
SYNCEN
Control of byte
alignment operation
7,8
V
CC
FAST
Power
Supply
Bipolar IC positive
power supply
10 to 19
D
OUT
a to j TTL out
Data output parallel 10
channels
20
RBCLK
TTL out
Read byte clock
21
PAROUT
Parity bit out
22
BSYNC
Byte synchronization
operation
23
PARERR
TTL out
Parity bit error
24, 25
V
CC
SLOW
Power
Supply
Logic positive power
supply
27
Loopsel a
TTL in
Test loop select
28
Loopsel b
29
RESREC
Receiver reset
30
RESFF
Reset all flip-flops
31
TBCLK
Transmit byte clock
32
PARIN
Parity bit in
33 to 42
D
IN
j to a
Data input parallel 10
channels
44
TESTCLK
Test clock. In test mode
this clock is the bit clock
46
TESTMOD
If this signal is low
TESTCLK is used
47
TXOFF
Transceiver off when log-
ical high
49, 50
V
CC
DRI
Power
Supply
LED driver positive
power supply
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