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參數(shù)資料
| 型號(hào)： | V320MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | V320 8-Bit Registered Bus Transceiver |
| 中文描述： | BICMOS SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 648K |
| 代理商： | V320MTC |
www.fairchildsemi.com
6
V
AC Electrical Characteristics
(
40
°
C to 85
°
C, V
CC
=
4.5V to 5.5V) 8 Output Switching
Note 6:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to outputs switching in the same direction also.
Note 7:
Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two
devices.
Note 8:
3-STATE delays are dominated by the RC Network (500
/ 250 pF, or 500
/ 500 pF) on the output and thus have been excluded from this
datasheet.
Symbol
From
(Input)
Mode
To
(Output)
Min
Typ
Max
Units
Output Load: C
L
=
50 pF, R
L
=
500
, 8 Outputs Switching
t
PLH
, t
PHL
CLKAB/CLKBA
Register
Bus A or B
1.5
6.6
ns
t
PLH
, t
PHL
Bus A or B
Transparent
Bus A or B
1.5
6.3
ns
t
PLH
, t
PHL
SELAB/SELBA
Select Bus
Bus A or B
1.5
6.6
ns
t
PLZ
, t
PHZ
OE
Output Disable
Bus A or B
1.5
6.6
ns
t
PZH
, t
PZL
OE
Output Enable
Bus A or B
1.5
6.6
ns
t
PLZ
, t
PHZ
Direction (D)
Dir. Disable
Bus A or B
1.5
6.6
ns
t
PZH
, t
PZL
Direction (D)
Dir. Enable
Bus A or B
1.5
7.6
ns
t
OSHL
Output to Output Skew (Note 6)
1.3
ns
t
OSHL
Output to Output Skew (Note 6)
1.1
ns
t
RISE
Transition Time, Outputs (1V to 2V)
0.5
1.5
ns
t
FALL
Transition Time, Outputs (1V to 2V)
0.4
1.9
ns
Output Load: C
L
=
250 pF, R
L
=
500
, 8 Outputs Switching
t
PLH
, t
PHL
CLKAB/CLKBA
Register
Bus A or B
2.5
11.2
ns
t
PLH
, t
PHL
Bus A or B
Transparent
Bus A or B
2.5
9.5
ns
t
PLH
, t
PHL
SELAB/SELBA
Select Bus
Bus A or B
2.5
11.2
ns
t
PLZ
, t
PHZ
OE
Output Disable
Bus A or B
(Note 8)
(Note 8)
ns
t
PZH
, t
PZL
OE
Output Enable
Bus A or B
2.5
11.5
ns
t
PLZ
, t
PHZ
Direction (D)
Dir. Disable
Bus A or B
(Note 8)
(Note 8)
ns
t
PZH
, t
PZL
Direction (D)
Dir. Enable
Bus A or B
2.5
13.5
ns
t
OSHL
Output to Output Skew (Note 8)
2.5
ns
t
OSLH
Output to Output Skew (Note 8)
2.0
ns
t
RISE
Transition Time, Outputs (1V to 2V)
2.0
5.5
ns
t
FALL
Transition Time, Outputs (1V to 2V)
1.4
4.4
ns
Output Load: C
L
=
500 pF, R
L
=
500
, 8 Outputs Switching
t
PLH
, t
PHL
CLKAB/CLKBA
Register
Bus A or B
3.5
17.0
ns
t
PLH
, t
PHL
Bus A or B
Transparent
Bus A or B
3.5
15.9
ns
t
PLH
, t
PHL
SELAB/SELBA
Select Bus
Bus A or B
3.5
17.0
ns
t
PLZ
, t
PHZ
OE
Output Disable
Bus A or B
(Note 8)
(Note 8)
ns
t
PZH
, t
PZL
OE
Output Enable
Bus A or B
3.5
18.5
ns
t
PLZ
, t
PHZ
Direction (D)
Dir. Disable
Bus A or B
(Note 8)
(Note 8)
ns
t
PZH
, t
PZL
Direction (D)
Dir. Enable
Bus A or B
3.5
22.3
ns
t
OSHL
Output to Output Skew (Note 6)
3.9
ns
t
OSLH
Output to Output Skew (Note 6)
3.1
ns
t
RISE
Transition Time, Outputs (1V to 2V)
4.4
7.8
ns
t
FALL
Transition Time, Outputs (1V to 2V)
2.5
6.6
ns
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| V320MTCX | 功能描述:總線收發(fā)器 Transceiver 8Bit Universal Bus RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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